creda
Uploaded by
51 SLIDES
718 VUES
510LIKES

Chapter One Introduction to Pipelined Processors

DESCRIPTION

Chapter One Introduction to Pipelined Processors. Principle of Designing Pipeline Processors. (Design Problems of Pipeline Processors). Job Sequencing and Collision Prevention. Job Sequencing and Collision Prevention . Consider reservation table given below at t=0.

1 / 51

Télécharger la présentation

Chapter One Introduction to Pipelined Processors

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Chapter One Introduction to Pipelined Processors

  2. Principle of Designing Pipeline Processors (Design Problems of Pipeline Processors)

  3. Job Sequencing and Collision Prevention

  4. Job Sequencing and Collision Prevention • Consider reservation table given below at t=0

  5. Job Sequencing and Collision Prevention • Consider next initiation made at t=1 • The second initiation easily fits in the reservation table

  6. Job Sequencing and Collision Prevention • Now consider the case when first initiation is made at t = 0 and second at t = 2. • Here both markings A1 and A2 falls in the same stage time units and is called collision and it must be avoided

  7. Terminologies

  8. Terminologies • Latency: Time difference between two initiations in units of clock period • Forbidden Latency: Latencies resulting in collision • Forbidden Latency Set: Set of all forbidden latencies

  9. General Method of finding Latency Considering all initiations: • Forbidden Latencies are 2 and 5

  10. Shortcut Method of finding Latency • Forbidden Latency Set = {0,5} U {0,2} U {0,2} = { 0, 2, 5 }

  11. Terminologies • Initiation Sequence : Sequence of time units at which initiation can be made without causing collision • Example : { 0,1,3,4 ….} • Latency Sequence : Sequence of latencies between successive initiations • Example : { 1,2,1….} • For a RT, number of valid initiations and latencies are infinite

  12. Terminologies • Initiation Rate : • The average number of initiations done per unit time • It is a positive fraction and maximum value of IR is 1 • Average Latency : Theaverage of latency of a given latency sequence AL = 1/IR

  13. Terminologies • Latency Cycle: • Among the infinite possible latency sequence, the periodic ones are significant. E.g. { 1, 3, 3, 1, 3, 3,… } • The subsequence that repeats itself is called latency cycle. E.g. {1, 3, 3}

  14. Terminologies • Period of cycle: The sum of latencies in a latency cycle (1+3+3=7) • Average Latency: The average taken over its latency cycle (AL=7/3=2.33) • To design a pipeline, we need a control strategy that maximize the throughput (no. of results per unit time) • Maximizing throughput is minimizing AL

  15. Terminologies • Control Strategy • Initiate pipeline as specified by latency sequence. • Latency sequence which is aperiodic in nature is impossible to design • Thus design problem is arriving at a latency cycle having minimal average latency.

  16. Terminologies • Stage Utilization Factor (SUF): • SUF of a particular stage is the fraction of time units the stage used while following a latency sequence. • Example: Consider 5 initiations of function A as below

  17. Terminologies • SUF of stage Sa is number of markings present along Sa divided by the time interval over which marking is counted. • SUF(Sa) = SUF(Sb) = SUF(Sc) = 10/14

  18. Terminologies • Let SU(i) be the stage utilization factor of stage i • Let N(i) be no. of markings against stage i in the reservation table • Suppose we initiate pipeline with initiation rate (IR), then SU(i) is given by

  19. SUF

  20. Terminologies • Minimum Average Latency (MAL) • Thus SU(i) = IR x N(i) • SU(i) ≤ 1  IR x N(i) ≤ 1 N(i) ≤ 1/IR  N(i) ≤ AL • Therefore

  21. State Diagram • Suppose a pipeline is initially empty and make an initiation at t = 0. • Now we need to check whether an initiation possible at t=i for i > 0. • bi is used to note possibility of initiation • bi = 1  initiation not possible • bi = 0  initiation possible

  22. State Diagram bi 1 0 1 0 0 1

  23. State Diagram • The above binary representation (binary vector) is called collision vector(CV) • The collision vector obtained after making first initiation is called initial collision vector(ICV) ICVA = (101001) • The graphical representation of states (CVs) that a pipeline can reach and the relation is given by state diagram

  24. State Diagram • States (CVs) are denoted by nodes • The node representing CVt-1 is connected to CVt by a directed graph from CVt-1 to CVt and similarly for CVt* with a * on arc

  25. Procedure to draw state diagram • Start with ICV • For each unprocessed state, say CVt-1, do as follows: • Find CVt from CVt-1 by the following steps • Left shift CVt-1 by 1 bit • Drop the leftmost bit • Append the bit 0 at the right-hand end

  26. Procedure to draw state diagram • If the 0th bit of CVt is 0, then obtain CV* by logically ORing CVt with ICV. • Make a new node for CVt and join with CVt-1 with an arc if the state CVt does not already exist. • If CV* exists, repeat step (c), but mark the arc with a *.

  27. State Diagram 1 0 1 0 0 1

  28. State Diagram 1 0 1 0 0 1 Left Shift 0 1 0 0 1 0

  29. State Diagram 1 0 1 0 0 1 Zero  CV* exists 01 0 0 1 0

  30. State Diagram 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 ICV – 101001 OR CVi – 010010 CV* 111011

  31. State Diagram 1 0 1 0 0 1 * Left Shift 0 1 0 0 1 0 1 1 1 0 1 1 Left Shift No CV* No CV* 1 0 0 1 0 0 1 1 0 1 1 0

  32. State Diagram 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 Left Shift * 1 0 0 1 0 0 1 1 0 1 1 0 Left Shift Zero  CV* exists No CV* 1 0 1 1 0 0 0 0 1 0 0 0 ICV – 101001 OR CVi – 001000 CV* 101001

  33. State Diagram 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 Zero  CV* exists * 0 1 0 0 0 0 1 1 1 0 0 1 ICV – 101001 CVi – 010000 CV* 111001

  34. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 Zero  CV* exists 0 0 1 0 0 0 * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 ICV – 101001 CVi – 011000 CV* 111001

  35. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 No CV*

  36. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 No CV*

  37. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  38. 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  39. 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  40. 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  41. State Diagram • From the above diagram, closed loops can be identified as latency cycles. • To find the latency corresponding to a loop, start with any initial * count the number of states before we encounter another * and reach back to initial *.

  42. 1 0 1 0 0 1 Latency = (3) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  43. 1 0 1 0 0 1 Latency = (1,3,3) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  44. 1 0 1 0 0 1 Latency = (4,3) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  45. 1 0 1 0 0 1 Latency = (1,6) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  46. 1 0 1 0 0 1 Latency = (1,7) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  47. 1 0 1 0 0 1 Latency = (4) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  48. 1 0 1 0 0 1 Latency = (6) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  49. 1 0 1 0 0 1 Latency = (7) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  50. State Diagram • The state with all zeros has a self-loop which corresponds to empty pipeline and it is possible to wait for indefinite number of latency cycles of the form (1,8), (1,9),(1,10) etc. • Simple Cycle: latency cycle in which each state is encountered only once. • Complex Cycle: consists of more than one simple cycle in it. • It is enough to look for simple cycles

More Related