Chapter One Introduction to Pipelined Processors

1. Chapter One Introduction to Pipelined Processors

2. Handler’s Classification • Based on the level of processing, the pipelined processors can be classified as: • Arithmetic Pipelining • Instruction Pipelining • Processor Pipelining

3. Arithmetic Pipelining • The arithmetic logic units of a computer can be segmented for pipelined operations in various data formats. • Example : Star 100

4. Arithmetic Pipelining

5. Arithmetic Pipelining • Example : Star 100 • It has two pipelines where arithmetic operations are performed • First: Floating Point Adder and Multiplier • Second : Multifunctional • All scalar instructions • Floating point adder, multiplier and divider. • Both pipelines are 64-bit and can be split into four 32-bit at the cost of precision

6. Star 100 Architecture

7. Instruction Pipelining • The execution of a stream of instructions can be pipelined by overlapping the execution of current instruction with the fetch, decode and operand fetch of the subsequent instructions • It is also called instruction look-ahead

8. Instruction Pipelining

9. Example : 8086 • The organization of 8086 into a separate BIU and EU allows the fetch and execute cycle to overlap. This is called pipelining.

10. Processor Pipelining • This refers to the processing of same data stream by a cascade of processors each of which processes a specific task • The data stream passes the first processor with results stored in a memory block which is also accessible by the second processor • The second processor then passes the refined results to the third and so on.

11. Processor Pipelining

12. Li and Ramamurthy's Classification • According to pipeline configurations and control strategies, Li and Ramamurthy classify pipelines under three schemes • Unifunction v/s Multi-function Pipelines • Static v/s Dynamic Pipelines • Scalar v/s Vector Pipelines

13. Uni-function v/s Multi-function Pipelines

14. Unifunctional Pipelines • A pipeline unit with fixed and dedicated function is called unifunctional. • Example: CRAY1 (Supercomputer - 1976) • It has 12 unifunctional pipelines described in four groups: • Address Functional Units: • Address Add Unit • Address Multiply Unit

15. Unifunctional Pipelines • Scalar Functional Units • Scalar Add Unit • Scalar Shift Unit • Scalar Logical Unit • Population/Leading Zero Count Unit • Vector Functional Units • Vector Add Unit • Vector Shift Unit • Vector Logical Unit

16. Unifunctional Pipelines • Floating Point Functional Units • Floating Point Add Unit • Floating Point Multiply Unit • Reciprocal Approximation Unit

17. Cray 1 : Architecture

19. Cray -1

20. Multifunctional A multifunction pipe may perform different functions either at different times or same time, by interconnecting different subset of stages in pipeline. Example 4X-TI-ASC (Supercomputer - 1973)

21. 4X-TI ASC It has four multifunction pipeline processors, each of which is reconfigurable for a variety of arithmetic or logic operations at different times. It is a four central processor comprised of nine units.

22. Multifunctional • It has • one instruction processing unit • four memory buffer units and • four arithmetic units. • Thus it provides four parallel execution pipelines below the IPU. • Any mixture of scalar and vector instructions can be executed simultaneously in four pipes.

23. Architecture Overview of 4X-TI ASC

24. Static Vs Dynamic Pipeline

25. Static Pipeline • It may assume only one functional configuration at a time • It can be either unifunctional or multifunctional • Static pipelines are preferred when instructions of same type are to be executed continuously • A unifunction pipe must be static.

26. Dynamic pipeline • It permits several functional configurations to exist simultaneously • A dynamic pipeline must be multi-functional • The dynamic configuration requires more elaborate control and sequencing mechanisms than static pipelining

27. Scalar Vs Vector Pipeline

28. Scalar Pipeline • It processes a sequence of scalar operands under the control of a DO loop • Instructions in a small DO loop are often prefetched into the instruction buffer. • The required scalar operands are moved into a data cache to continuously supply the pipeline with operands • Example: IBM System/360 Model 91

29. IBM System/360 Model 91 • In this computer, buffering plays a major role. • Instruction fetch buffering: • provide the capacity to hold program loops of meaningful size. • Upon encountering a loop which fits, the buffer locks onto the loop and subsequent branching requires less time. • Operand fetch buffering: • provide a queue into which storage can dump operands and execution units can fetch operands. • This improves operand fetching for storage-to-register and storage-to-storage instruction types.

30. Architecture overview of IBM 360/Model 91

32. Vector Pipelines • They are specially designed to handle vector instructions over vector operands. • Computers having vector instructions are called vector processors. • The design of a vector pipeline is expanded from that of a scalar pipeline. • The handling of vector operands in vector pipelines is under firmware and hardware control. • Example : Cray 1

34. Linear pipeline (Static & Unifunctional) • In a linear pipeline data flows from one stage to another and all stages are used once in a computation and it is for one functional evaluation.

35. Non-linear pipeline • In floating point adder, stage (2) and (4) needs a shift register. • We can use the same shift register and then there will be only 3 stages. • Then we should have a feedback from third stage to second stage. • Further the same pipeline can be used to perform fixed point addition. • A pipeline with feed-forward and/or feedback connections is called non-linear

36. Example: 3-stage nonlinear pipeline

37. 3 stage non-linear pipeline Output A • It has 3 stages Sa, Sb and Sc and latches. • Multiplexers(cross circles) can take more than one input and pass one of the inputs to output • Output of stages has been tapped and used forfeedback and feed-forward. Output B Input Sa Sb Sc

38. 3 stage non-linear pipeline • The above pipeline can perform a variety of functions. • Each functional evaluation can be represented by a particular sequence of usage of stages. • Some examples are: • Sa, Sb, Sc • Sa, Sb, Sc, Sb, Sc, Sa • Sa, Sc, Sb, Sa, Sb, Sc

39. Reservation Table • Each functional evaluation can be represented using a diagram called Reservation Table(rt). • It is the space-time diagram of a pipeline corresponding to one functional evaluation. • X axis – time units • Y axis – stages

40. Reservation Table • For first sequence Sa, Sb, Sc, Sb, Sc, Sa called function A , we have

41. Reservation Table • For second sequence Sa, Sc, Sb, Sa, Sb, Sc called function B, we have

42. 3 stage non-linear pipeline Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

43. Function A

44. 3 stage pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

45. 3 stage pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

46. 3 stage pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

47. 3 stage pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

48. 3 stage pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

49. 3 stage pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Output B Input Sa Sb Sc Reservation Table Time  Stage 

50. Function B