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CSE 378 Computer Hardware Design (Formerly, Design of Digital Systems)

CSE 378 Computer Hardware Design (Formerly, Design of Digital Systems). Prof. Richard E. Haskell Email: haskell@oakland.edu Tel: 248-370-2861 Web site: www.cse.secs.oakland.edu/haskell Follow VHDL -> CSE 378 link Office Hours: Mon. and Wed., 3:00 - 4:00 p.m. 115 Dodge Hall.

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CSE 378 Computer Hardware Design (Formerly, Design of Digital Systems)

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  1. CSE 378Computer Hardware Design(Formerly, Design of Digital Systems) • Prof. Richard E. Haskell • Email: haskell@oakland.edu • Tel: 248-370-2861 • Web site: www.cse.secs.oakland.edu/haskell • Follow VHDL -> CSE 378 link • Office Hours: • Mon. and Wed., 3:00 - 4:00 p.m. • 115 Dodge Hall

  2. CSE 378 Computer Hardware Design • Lecture: 10:00 - 11:47 p.m., Tues., Thurs. • Room: 214 Elliott Hall • Macomb University Center – via TV • Lab: 2:30 - 5:30 p.m., Mon. or Wed. or 12:00 - 3:00 p.m., Tues. • Room: 133 SEB or 12:00 - 3:00 p.m., Thurs. at Macomb Univ. Center

  3. Course Goals • Learn to design digital systems using VHDL • Learn to synthesize VHDL designs to Xilinx Spartan II series FPGAs • Learn to use VHDL design tools: • Xilinx ISE 4.2i • Aldec Active-HDL Simulator • Learn to design a small microcontroller

  4. Course Objectives • Design combinational circuits using VHDL • Design sequential circuits using VHDL • Synthesize VHDL designs to Xilinx FPGAs • Simulate VHDL designs using Aldec Active-HDL • Design a stack-based microcontroller using VHDL and synthesize it to a Xilinx FPGA

  5. List of Topics • Digital Computers and Information • Combinational Logic Circuits & Design • Sequential Circuits • Registers and Counters • RAMs and ROMs • Xilinx FPGAs • Register Transfers and Datapaths • Sequencing and Control • Design of a stack-based microprocessor

  6. Labs • 1. Multiplexers -- Active-HDL 5.1 Simulation and Xilinx Synthesis • 2. ALU1 – Shifting, Increment and Decrement Instructions • 3. ALU2 – Arithmetic and Logic Instructions • 4. ALU3 – Comparators, 7-Segment Displays and Counters • 5. A Single-Cycle Processor (Registers, Function Unit, ROM)

  7. Labs (cont.) • 6. Program Counter and Program Control • 7. Data Stack -- Data Stack Instructions • 8. Return Stack -- Subroutines --A Software UART • 9. The WC16 Core -- Multiplication and Division -- DIO2 Board

  8. Course Web Site • Course materials can be downloaded from the following course website • www.cse.secs.oakland.edu/haskell/ • follow the VHDL -> CSE 378 link

  9. Grading based on • Labs -- 20% • 9 Labs will be assigned to be demonstrated and handed in. • Homework -- 5% • 2 Exams -- 25% each • VHDL project • Project design -- 10% • Written report -- 10% • Oral Presentation -- 5%

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