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Innovative Virtual Wallet Design for Enhanced Shopping Experience

This project, completed on October 5, 2009, focuses on creating a handheld device aimed at optimizing budgeting and improving the shopping experience. Developed by Gates Winkler, Jordan Samuel Fei, and Yin Shen, the device integrates various functionalities including budget assistance, cost estimation, and transaction tracking. Key components of the design include structural Verilog coding, behavioral modeling, and testing through various simulations. The project culminates in a comprehensive proposal, complete with flow charts, floor plans, and systematic testing of adders and subtractors.

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Innovative Virtual Wallet Design for Enhanced Shopping Experience

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  1. Virtual WalletStructural Design • Gates Winkler • Jordan Samuel Fei • Yin Shen • October 5, 2009 To create a handheld device which will save money and time through budget assistance and improve the shopping experience.

  2. Status Finished • Flow Chart • Behavioral Verilog • Transistor Estimate • Floor Plan • Structure Proposal • Structural Verilog To Do • Schematic • Layout • Testing

  3. Adder

  4. Verilog:adder # Loading work.addex_test # Loading work.rca30 # Loading work.fadd # run -all ; quit # __ excess-127 tests __ # # 0 + 5 = 5 ovf:0 # # 20 + 35 = 55 ovf:0 # # 100 + 1 = 101 ovf:0 # # ** Note: $finish : structural_adder.v(86) # Time: 3 us Iteration: 0 Instance: /addex_test

  5. Verilog:subtractor # Loading work.sub_test # Loading work.sv30bSub # Loading work.fsub # run -all ; quit # __ excess-127 tests __ # # 5 - 0 = 5 ovf:0 # # 100 - 35 = 65 ovf:0 # # 1523 - 6 = 1517 ovf:0 # # ** Note: $finish : structural_subtractor.v(87) # Time: 3 us Iteration: 0 Instance: /sub_test

  6. Verilog:flip-flop # Loading work.testbench # Loading work.dtype # run -all ; quit # 0 clk = 0, D=0, nRst = 1, Q = x, nQ =x # 10 clk = 1, D=0, nRst = 1, Q = 0, nQ =1 # 20 clk = 0, D=0, nRst = 1, Q = 0, nQ =1 # 30 clk = 1, D=0, nRst = 1, Q = 0, nQ =1 # 40 clk = 0, D=1, nRst = 1, Q = 0, nQ =1 # 50 clk = 1, D=1, nRst = 1, Q = 1, nQ =0 # 60 clk = 0, D=1, nRst = 1, Q = 1, nQ =0 # 70 clk = 1, D=1, nRst = 1, Q = 1, nQ =0 # 80 clk = 0, D=0, nRst = 1, Q = 1, nQ =0 # 90 clk = 1, D=0, nRst = 1, Q = 0, nQ =1 # 100 clk = 0, D=1, nRst = 1, Q = 0, nQ =1 # 110 clk = 1, D=1, nRst = 1, Q = 1, nQ =0 # 120 clk = 0, D=0, nRst = 1, Q = 1, nQ =0 # 130 clk = 1, D=0, nRst = 1, Q = 0, nQ =1 # ** Note: $finish : dff.v(56) # Time: 131 ns Iteration: 0 Instance: /testbench

  7. Verilog:right shift # Loading work.test_rtshift # Loading work.rtShift # Loading work.dtype # run -all ; quit # 0 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 10 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 20 clk = 0, out = 000000000000000000000000000000, A=0, rst=0 # 30 clk = 1, out = 000000000000000000000000000000, A=0, rst=0 # 40 clk = 0, out = 000000000000000000000000000000, A=0, rst=1 # 50 clk = 1, out = 000000000000000000000000000000, A=0, rst=1 # 60 clk = 0, out = 000000000000000000000000000000, A=1, rst=1 # 70 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1, A=1, rst=1 # 80 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 90 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 100 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 110 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 120 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 130 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 140 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 150 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 160 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 170 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=0, rst=1 # 180 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=1, rst=1 # 190 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1, A=1, rst=1 # 200 clk = 0, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, A=1, rst=1 # 210 clk = 1, out = xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1, A=1, rst=1 # ** Note: $finish : Right_Shift.v(186) # Time: 211 ns Iteration: 0 Instance: /test_rtshift

  8. Verilog:right shift

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