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Sequential Implementation CSCi 2021: Computer Architecture and Organization

Carnegie Mellon. Carnegie Mellon. Sequential Implementation CSCi 2021: Computer Architecture and Organization. Chap. 4.3. Last Time. Hardware logic design concepts Boolean algebra, logic units, building blocks HCL. Carnegie Mellon. Today. Sequential processor implementation

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Sequential Implementation CSCi 2021: Computer Architecture and Organization

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  1. Carnegie Mellon Carnegie Mellon Sequential ImplementationCSCi 2021: Computer Architecture and Organization Chap. 4.3

  2. Last Time • Hardware logic design concepts • Boolean algebra, logic units, building blocks • HCL

  3. Carnegie Mellon Today • Sequential processor implementation • Instruction execution • HW #3 will be out today

  4. Byte 0 1 2 3 4 5 nop 0 0 addl 6 0 halt 1 0 subl 6 1 rrmovlrA, rB 2 0 rA rB andl 6 2 irmovlV, rB 3 0 8 rB V xorl 6 3 rmmovlrA, D(rB) 4 0 rA rB D jmp 7 0 mrmovlD(rB), rA 5 0 rA rB D jle 7 1 OPlrA, rB 6 fn rA rB jl 7 2 jXXDest 7 fn Dest je 7 3 call Dest 8 0 Dest jne 7 4 ret 9 0 jge 7 5 pushlrA A 0 rA 8 jg 7 6 poplrA B 0 rA 8 Y86 Instruction Set

  5. valA Register file srcA A valW W dstW valB srcB B Clock fun A MUX 0 A L U = B 1 Clock Building Blocks A • Combinational Logic • Compute Boolean functions of inputs • Continuously respond to input changes • Operate on data and implement control • Storage Elements • Store bits • Addressable memories • Named registers • Loaded only as clock rises B A B

  6. Hardware Control Language • Very simple hardware description language • Can only express limited aspects of hardware operation • Parts we want to explore and modify • Data Types • bool: Boolean • a, b, c, … • int: words • A, B, C, … • Does not specify word size---bytes, 32-bit words, … • Statements • bool a = bool-expr; • int A = int-expr;

  7. HCL Operations • Classify by type of value returned • Boolean Expressions • Logic Operations (bits) • a && b, a || b, !a • Word Comparisons • A == B, A != B, A < B, A <= B, A >= B, A > B • Set Membership • A in { B, C, D } • Same as A == B || A == C || A == D • Word Expressions • Case expressions • [ a : A; b : B; c : C ] • Evaluate test expressions a, b, c, … in sequence • Return word expression A, B, C, … for first successful test

  8. SEQ Hardware Structure • State • Program counter register (PC) • Condition code register (CC) • Register File • Memories • Access same memory space • Data: for reading/writing program data • Instruction: for reading instructions • Instruction Flow • Read instruction at address specified by PC • Process through stages • Update program counter

  9. newPC PC SEQ Stages valE , valM Write back valM • Fetch • Read/parse instruction from instruction memory • Decode • Read program registers • Execute • Compute value or address • Memory • Read or write data • Write Back • Write program registers • PC • Update program counter Data Data Memory memory memory Addr , Data valE CC CC ALU ALU Execute Bch aluA , aluB valA valB , srcA , srcB Decode A A B B dstA , dstB M M Register Register Register Register file file file file E E icode , ifun valP rA , rB valC Instruction PC Instruction PC memory increment Fetch memory increment PC

  10. Optional Optional D icode 5 0 rA rB ifun rA rB valC Instruction Decoding • Instruction Format • Instruction byte icode:ifun • Optional register byte rA:rB • Optional constant word valC

  11. Fetch Fetch 1 initially … Read 2 bytes Decode Read operand registers Execute Perform operation Set condition codes Memory Do nothing Write back Update register PC Update Increment PC by 2 OPlrA, rB 6 fn rA rB Executing Arith./Logical Operation

  12. Fetch icode:ifun M1[PC] Read instruction byte rA:rB M1[PC+1] Read register byte valP PC+2 Compute next PC Decode valA R[rA] Read operand A valB R[rB] Read operand B Execute valE valB OP valA Perform ALU operation Set CC Set condition code register Memory Write back R[rB]  valE Write back result PC update PC  valP Update PC Stage Computation: Arith/Log. Ops OPlrA, rB • Formulate instruction execution as sequence of simple steps • Use same general form for all instructions

  13. Fetch Read 2 bytes Decode Read stack pointer Execute Increment stack pointer by 4 Memory Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2 poplrA b rA 0 8 Executing popl

  14. Fetch icode:ifun M1[PC] Read instruction byte rA:rB M1[PC+1] Read register byte valP PC+2 Compute next PC Decode valA R[%esp] Read stack pointer valB R [%esp] Read stack pointer Execute valE valB + 4 Increment stack pointer Memory valM M4[valA] Read from stack Write back R[%esp]  valE Update stack pointer R[rA] valM Write back result PC update PC  valP Update PC Stage Computation: popl poplrA • Use ALU to increment stack pointer • Must update two registers • Popped value • New stack pointer

  15. Fetch Read 5 bytes Increment PC by 5 Decode Do nothing Execute Determine whether to take branch based on jump condition and condition codes Memory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch jXXDest Dest Not taken fall thru: Dest target: Taken 7 XX XX fn XX XX Executing Jumps

  16. Fetch icode:ifun M1[PC] Read instruction byte valC M4[PC+1] Read destination address valP PC+5 Fall through address Decode Execute Bch Cond(CC,ifun) Take branch? Memory Write back PC update PC  Bch ? valC : valP Update PC Stage Computation: Jumps jXXDest • Compute both addresses • Choose based on setting of condition codes and branch condition

  17. Fetch Read 5 bytes Increment PC by 5 Decode Read stack pointer Execute Decrement stack pointer by 4 Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest callDest Dest return: Dest target: 8 XX XX 0 XX XX Executing call

  18. Fetch icode:ifun M1[PC] Read instruction byte valC M4[PC+1] Read destination address valP PC+5 Compute return point Decode valB R[%esp] Read stack pointer Execute valE valB + –4 Decrement stack pointer Memory M4[valE] valP Write return value on stack Write back R[%esp]  valE Update stack pointer PC update PC  valC Set PC to destination Stage Computation: call callDest • Use ALU to decrement stack pointer • Store incremented PC

  19. Fetch icode:ifun M1[PC] valC M4[PC+1] valP PC+5 Decode valB R[%esp] Execute valE valB + –4 Memory M4[valE] valP Write back R[%esp]  valE PC update PC  valC call 0x049 Specific values w/r to this code callDest

  20. 0x000: 30f209000000 0x006: 30f315000000 0x00c: 6123 0x00e: 30f480000000 irmovl $128, %esp 0x014: 404364000000 0x01a: a02f 0x01c: b00f 0x01e: 7348000000 0x023: 8049000000 0x028: … … 0x048: 00 halt 0x049: … … 0x099: 90 ret

  21. Fetch Logic • Predefined Blocks • PC: Register containing PC • Instruction memory: Read 6 bytes (PC to PC+5) • Split: Divide instruction byte into icode and ifun • Align: Get fields for rA, rB, and valC

  22. Fetch Control Logic boolneed_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; boolinstr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };

  23. Decode Logic • Register File • Read ports A, B • Write ports E, M • Addresses are register IDs or 8 (none) • Control Logic • srcA, srcB: read port addresses • dstA, dstB: write port addresses

  24. OPlrA, rB Decode valA R[rA] Read operand A rmmovlrA, D(rB) Decode valA R[rA] Read operand A poplrA Decode valA R[%esp] Read stack pointer jXXDest Decode No operand callDest Decode No operand ret Decode valA R[%esp] Read stack pointer A Source intsrcA = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : rA; icode in { IPOPL, IRET } : RESP; // REgister Stack Pointer 1 : RNONE; # Don't need register ];

  25. OPlrA, rB Write-back R[rB]  valE Write back result rmmovlrA, D(rB) Write-back None poplrA Write-back R[%esp]  valE Update stack pointer jXXDest Write-back None callDest Write-back R[%esp]  valE Update stack pointer ret Write-back R[%esp]  valE Update stack pointer E Destination intdstE = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rB; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ];

  26. SEQ Summary • Implementation • Express every instruction as series of simple steps • Follow same general flow for each instruction type • Assemble registers, memories, predesigned combinational blocks • Connect with control logic • Limitations • Too slow to be practical • In one cycle, must propagate through instruction memory, register file, ALU, and data memory • Would need to run clock very slowly

  27. Next Time • Pipeline implementation • Chap. 4.4

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