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Integer Multiplication and Division. An Animated Illustration. Start. Multiplier0 = 1. Multiplier0 = 0. Test Multiplier bit 0. Add Multiplicand to Product and place result in Product Register. Shift Multiplicand register left 1 bit. Shift Multiplier register right 1 bit. No. Yes.
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Integer Multiplication and Division An Animated Illustration
Start Multiplier0 = 1 Multiplier0 = 0 Test Multiplier bit 0 Add Multiplicand to Product and place result in Product Register Shift Multiplicand register left 1 bit Shift Multiplier register right 1 bit No Yes 32nd repetition? Done Integer Multiplication Multiplication Algorithm
Next two times: Right-most bit of multiplier is 0 sll Multiplicand slr Multiplier The result (15) is found in the product register. Note! In 4-bit arithmetic this product is too big and results in an overflow. sll Multiplicand slr Multiplier sll Multiplicand srl Multiplier Right-most bit of Multiplier is 1 Product += Multiplicand Right-most bit of multiplier is 1 Product += Multiplicand Multiplicand 1 1 0 1 0 0 1 0 1 0 Multiplier 8-bit ALU 0 0 Product Control 1 1 1 1 Integer Multiplication Consider the Multiplication of 4-bit numbers Convert to binary and place in registers Multiply 5 by 3 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0
Fast Multiplication Hardware Mplier1*Mcand Mplier0*Mcand 32 bits Instead of using a single 32-bit adder 32 times, this hardware uses 32 32-bit adders to “unroll the loop” in the algorithm and perform the multiplication in 1 iteration. Mplier2*Mcand 32 bits 1 bit Mplier3*Mcand 32 bits 1 bit 32 bits 1 bit Mplier31*Mcand 32 bits 32 bits 1 bit Prod2 Prod1 Prod0 Prod63..32 Prod31
Start Subtract Divisor register from Remainder register and store result in Remainder register Yes No Remainder > 0 Restore the original remainder by adding the Divisor register to the Remainder register. Shift the Quotient register to the left setting new rightmost bit to 0. Shift Quotient register to lef setting the new rightmost bit to 1 Shift Divisor register 1 bit right No Yes 33rd repetition? Done Integer Division Division Algorithm
srl Divisor, then subtract, restore, srl once more. Quotient is still 0 and Divisor register is now: Subtract divisor from remainder 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 1 1 Once more subtract Divisor from Remainder: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 Subtract Divisor from Remainder 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 srl Divisor and repeat subtract 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 DONE Division is completed after the Divisor has been shifted right four times. New remainder New remainder New Remainder New remainder Divisor 0 0 0 1 1 0 1 1 Quotient 8-bit ALU 1 1 0 Remainder Control 0 0 Integer Division Consider division of 4-bit numbers First convert to binary an load dividend into the “Remainder” register and divisor into the left half of the “Divisor” register. The “Quotient” register initially contains all 0’s. If the result is negative, restore (add divisor and remainder and store result in remainder) Divide 7 by 3 Remainder is positive: sll and add 1 in Quotient srl Divisor Again, result is negative. Restore the remainder and shift left 0 in Quotient. Once again the result is negative. Restore the previous Remainder and sll the quotient. 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
