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Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester PowerPoint Presentation
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Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester

Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester

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Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester

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  1. Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

  2. SMP reminder Frames Flags I. SMP Tester Hardware CERN, the LHC and Machine Protection

  3. Notions (1): Frames and flags Frames transmission Electronic board Electronic board 1 0 1 0 1 1 0 1 0 0 1 ME MD 32 bits ≈ 100us Manchester Encoder Manchester Decoder Flags transmission Electronic board Electronic board 0 or 1 1 bit < 1us I. SMP Tester Hardware CERN, the LHC and Machine Protection

  4. Notions (2): FPGA memories Registers History buffer (HB) 32 bits 128 bits 1024 records I. SMP Tester Hardware CERN, the LHC and Machine Protection

  5. HW tester simulation BCTs CIBFU CIBFC CIBFU CIBFC LHC BIS CIBFU CIBFC CIBU BEMs CIBFU CIBFC CIBFU CIBFC CIBFU CIBFC CISC CISV BETS BPF En, Int DCCT SMPC CISR A CISR B CISGL A CISGL B CISA GMT Electrical-differential RS485 Current loops Optical Manchester encoded frames BPF SBF Flags CIBFU CIBFC 5 CISTR 2 CISTCL 1 CISTA CIBFU CIBFC SPS Ext BIS CIBFU CIBFC CIBFU CIBFC I. SMP Tester Hardware CERN, the LHC and Machine Protection

  6. HW tester connections C I S C I. SMP Tester Hardware CERN, the LHC and Machine Protection

  7. Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

  8. Historic Developments Version 1: until August 2011 Version 2: from May to October 2011 Version 3: from November 2011 (to May 2012?) II. Short historic CERN, the LHC and Machine Protection

  9. Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

  10. Version 1: Layers overview Excel Command Results LabExcel SMPCTester LabVIEW FESA vi FESA dll FESA Ethernet communication PowerPC (FESA drivers) VME boards Electronic cards III. Version 1 - LabVIEW tester CERN, the LHC and Machine Protection

  11. Version 1: Test steps • Main limitation: • New test => New LabVIEW code ! Command Results LabExcel SMPCTester FESA vi FESA dll Ethernet communication PowerPC (FESA drivers) Command Results LabExcel Electronic cards SMPCTester VME bus FESA vi FESA dll Ethernet communication PowerPC (FESA drivers) Electronic cards III. Version 1 - LabVIEW tester CERN, the LHC and Machine Protection

  12. Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

  13. Version 2: Brain storming Goal 1: Add/modify tests out of LabVIEW => Tests defined in Excel A test  Operations to perform How many possible operations? => 7 Set Wait Goal 2: Separate the test operations of the test validation Get SMP controller Test program Generate inputs from Excel command Yes = Test success • Simulates at every time (ms granularity): • The output signals • The internal memory (only registers) Expected behavior calculation => Birth of the Virtual SMP controller IV. Version 2 - Generic test and virtual SMPC CERN, the LHC and Machine Protection

  14. Version 2: Code overview SMP controller Test program Generate inputs from Excel command Yes = Test success Expected behavior calculation IV. Version 2 - Generic test and virtual SMPC CERN, the LHC and Machine Protection

  15. Version 2: User’s interface Ctrl + Click Shift + Click Ctrl + Shift + Click IV. Version 2 - Generic test and virtual SMPC CERN, the LHC and Machine Protection

  16. Version 2: Limitations - Maintain the Virtual SMPC code (not really an issue) - Implementation of the History Buffer behavior - Very slow: 1Hz(FESA subscription / FESA refresh) • total time 120 tests: • SMPC = 6h 40m • VSMPC = 1h 20m • 1. Formal Methods ? • CISR model • CISGL too complex BPF CISR input headers Energy priority 2. Accelerate FESA refresh at 10Hz? => PowerPC overloaded… IV. Version 2 - Generic test and virtual SMPC CERN, the LHC and Machine Protection

  17. Plan Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed Safe Machine Parameters - Tester SMP Tester Hardware Short Historic Version 1 - LabVIEW tester Version 2 - Generic test and virtual SMPC Version 3 - Need for speed CERN, the LHC and Machine Protection

  18. Version 3: Requirement • The virtual SMP has to be removed (cannot be faster) • => Expected values for registers and HB have to be in Excel • FESA must be replaced • => Nodal? Too basic, old, no support… • => c code implementation ! Excel Command Results LabExcel SMPCTester LabVIEW Developped under Visual Studio FESA vi Socket implementation (with Jean-Christophe’s help) C dll FESA dll Server client FESA Ethernet communication Ethernet (TCP protocol) • c function to access boards memories (provided by Ben) • .h libraries search (J-C’s help) PowerPC (c server) PowerPC (FESA drivers) VME boards Electronic cards V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  19. Version 3: Timing Performances Test protocol: - Read from LabVIEW a bloc of memory = (32*Nb registers read) bits => One 32-bits register read in 2 microseconds => 1ms offset due to the socket connection V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  20. Version 3: Timing management • Each VME-crate has a server running → time synchronization needed • How to implement the Wait function? • Use of c functions (rdtsc, usleep, nanosleep, …)? They are system dependant • Use of the UTC time in the FPGA registers. 2 registers in each board: • - UTC_SECOND : set by the tester through the socket • UTC_MICROSECOND : set to 0 each pulse on pps boards input (lemo cable, few nanoseconds precision). Timing error 2us 1000us Wait (1000us) Read reg 0 1000 t [us] Still subject to system interruptions! => Timing error generation V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  21. Version 3: Tests operations Tester 2 (7 op): -Send frame -Send flag -Write register -Read register -Read signal -Read HB -Wait Tester 3 (9 op): -Set frame -Set flag -Enable generators -Write register -Read register -HB Start read -HB Get records -Wait -For: repeats a set of operations (reduce socket data transfer) • Get info back: • Compare with expected (Excel) • HB interpretation* • Generate timing error Need for synchronization Only last events • *HB interpretation: • Presence of record • Record data expected (energy value, control status…) • Time spent between specific records (CISR validity input) V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  22. Version 3: Example (CISR headers) General Goal: Test the channel 1 energy input on CISRA of the LHC SMPC 8 bits = 2 hexa 1 input frame = HDR Energy CRC Valid header: x92 32 bits • Specific goals (from specification): • Test all 256 headers and check the Valid flag (1 bit in a register) is true only for x92 • Check the validity time is 7 times the energy frame period • Test steps: • Send each header once, period T=1000us between each frame • Check the valid flag is false for all except x92 (check done tc=200us after the frame sending) • Check the flag stays true 7*T=7000us x93 x94 … xFF x00 … x91 x92 T T T 7*T t [us] tc FALSE FALSE Valid Flag TRUE V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  23. Version 3: Example (CISR headers) x93 x94 … xFF x00 … x91 x92 T T T 7*T t [us] tc Time spent: 5600 + 200 + 1000*255 + 7000 = 267 800 us FALSE FALSE Valid Flag TRUE 12 to 13 min VS 0.3 seconds V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  24. Version 3: Limitations None ? V. Version 3 - Need for speed CERN, the LHC and Machine Protection

  25. Version 3: ToDo END ! • Low level implementation (c): • History Buffer interpretation • Remove text file between LabVIEW and the c dll • Tests definition (Excel): • Re-define all tests (4/120 done). For both SPS and LHC • Add the CISC tests • High level language (LabVIEW, LabWindowsCVI, Java…): • Design the tests viewer • Develop a test builder V. Version 3 - Need for speed CERN, the LHC and Machine Protection