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ARM Instructions Encoding Formats

Learn how ARM instructions are encoded with condition field codes like EQ, NE, CS/HS, CC/LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL.

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ARM Instructions Encoding Formats

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  1. Please see “portrait orientation” PowerPoint file for Appendix B Figure B.1. ARM instructions encoding formats.

  2. . . . T ABLE B.1 Condition field encoding in ARM instructions Condition Condition Name Condition co de field suffix test b b 31 28 0 0 0 0 EQ Equal (zero) Z = 1 0 0 0 1 NE Not equal (nonzero) Z = 0 0 0 1 0 CS/HS Carry set/Unsigned higher or same C = 1 0 0 1 1 CC/LO Carry clear/Unsigned lo w er C = 0 0 1 0 0 MI Min us (negative) N = 1 0 1 0 1 PL Plus (p ositiv e or zero) N = 0 0 1 1 0 VS Ov erflo w V = 1 0 1 1 1 VC No o v erflo w V = 0  1 0 0 0 HI Unsigned higher C Z = 0  1 0 0 1 LS Unsigned lo w er or same C Z = 1  1 0 1 0 GE Signed greater than or equal N V = 0  1 0 1 1 L T Signed less than N V = 1   1 1 0 0 GT Signed greater than Z (N V) = 0   1 1 0 1 LE Signed less than or equal Z (N V) = 1 1 1 1 0 AL Alw a ys 1 1 1 1 Not used

  3. Please see “portrait orientation” PowerPoint file for Appendix B Table B.2. ARM arithmetic instructions

  4. Please see “portrait orientation” PowerPoint file for Appendix B Table B.3. ARM logic, compare, test, and move instructions

  5. T ABLE B.4 ARM instructions for single word or byte transfer from/to memory Mnemonic Instruction Operation (Name) bits p erformed B L  LDR 0 1 R d [EA] (Load w ord)  LDRB 1 1 R d [EA] (Load b yte)  STR 0 0 EA [R d ] (Store w ord)  STRB 1 0 EA [R d ] (Store b yte)

  6. Please see “portrait orientation” PowerPoint file for Appendix B Table B.5. ARM instructions for multiple word transfers from/to memory

  7. Please see “portrait orientation” PowerPoint file for Appendix B Table B.6. ARM instructions for status register transfers, software interrupt, and data swap.

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