CSCE 430: Computer Architecture Final Project

1. CSCE 430: Computer Architecture Final Project • Group E: • Matt Horn • Dongpu Jin • Nick Briganti • Sean Hicks

2. Overview

3. Overview • 3 stage pipeline • LCD panel output • Static “branch not taken” predictor • Write through Instruction and Data Caches • Versatile assembler for rapid development

4. Pipeline • Three stages pipeline • IF/ID • EX • MEM/WB • Two pipeline registers • ID/EX register • EX/MEM register

5. Pipeline • Save both signal and data for next stage • Synchronous • Clock in values on the rising edge • Clock cannot be too fast, because of tsu and th

6. Forwarding Unit • Data hazards happens because of data dependency • lw r1 0 • addi r2 r1 2 • Need to forward value for lw directly to ALU source

7. Forwarding Unit • IF (WRITE) and (rt = Dest) then ForwardA = 1 • IF (WRITE) and (rd= Dest) then ForwardB = 1

8. Hazard Detection • Handles cases where Forwarding Unit is not enough • -- Ex: lw $s0 0($0) • add $s2 $s0 $s1 • Inserts Noops by deasserting control signals and stalls PC in order to halt pipeline

9. Branch Predictor • Static “Branch not Taken” predictor • Deasserts control signals for pipeline when a branch is taken • Otherwise, instructions continue to execute • Penalty for correct branch = 0 cycles • Penalty for an incorrect branch = 2 cycles

10. Instruction Cache • 16 sets, 4 words/block • Direct mapped • Address Breakdown • 4 bit tag • 4 bit index • 2 bit offset • 8 cycle penalty

11. Instruction Cache

12. Data Cache • Same specs as instruction cache except • 2 bit tag • Write-through policy • 8 cycle delay for read miss • 9 cycle delay for write miss

13. Data Cache

14. Overall Verification

15. LCD Panel • Includes 128 words which mirror data memory • Handles most user IO for the board • User selects location 0-127 with switches • LCD Panel displays MEM[0-127]

16. LCD Panel • Advantages of LCD memory mirroring data • Simplifies program development • Aids debugging on the board • Disadvantages • Less versatile, displayed data must appear in memory locations 0-127

17. Assembler • Final instruction set

18. Assembler • Data driven, ISA parsed before assembly • Instruction set • Tokens • Registers

19. Assembler - Instructions • add rd,rs,rt; op=0, rs, rt, rd, shamt=0, funct=32 • addirs, rt, imm; op=8, rt, rs, imm • luirs, imm; op=15, rs, rt=0, imm • bners, rt, imm; op=5, rs, rt, ~imm • jal label; op=3, label • jrrs; op=0, rs, rt=0, rd=0, shamt=0, funct=8

20. Assembler - Tokens • rd 5 • rs 5 • rt 5 • op 6 • imm +16 • label +26 • shamt 5 • funct 6

21. Assembler - Registers • zero 0 • 0 0 • at 1 • v0 2 • v1 3 • a0 4 • a1 5 • a2 6 • a3 7 • t0 8

22. Assembler - Output • # Reads memory location 0, then sorts that many numbers in the following memory values 1-n • main: • lw $s1 0 $0 # load memory location 0 into $s1 • addi $s1 $s1 1 # increment $s1 for comparison with our "for" loop • outer: • addi $s0 $0 0 # s0 is != 0 if a value has been changed during a bubble sort sweep • addi $s2 $0 1 # s2 holds the current outer iteration of bubble sort BEGIN 0: 8C110000; -- lw 17 0 0 1: 22310001; -- addi 17 17 1 2: 20100000; -- addi 16 0 0 3: 20120001; -- addi 18 0 1 4: 20120001; -- addi 18 0 1 5: 8E48FFFF; -- lw 8 -1 18 6: 8E490000; -- lw 9 0 18 7: 01285022; -- sub 10 9 8 8: 3D608000; -- lui 11 -32768 9: 016A6024; -- and 12 11 10

23. Questions?