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Data Hazards and Multistage Pipeline Arvind Computer Science & Artificial Intelligence Lab.

Data Hazards and Multistage Pipeline Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology. Three-Stage SMIPS. Register File. Epoch. stall?. PC. Execute. Decode. wbr. fr. +4. Data Memory. Inst Memory. Three-Stage SMIPS.

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Data Hazards and Multistage Pipeline Arvind Computer Science & Artificial Intelligence Lab.

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  1. Data Hazards and Multistage Pipeline Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology http://csg.csail.mit.edu/SNU

  2. Three-Stage SMIPS Register File Epoch stall? PC Execute Decode wbr fr +4 Data Memory Inst Memory http://csg.csail.mit.edu/SNU

  3. Three-Stage SMIPS modulemkProc(Proc); Reg#(Addr) pc <- mkRegU; Reg#(Bool) epoch <- mkRegU; RFilerf <- mkRFile; Memory mem <- mkTwoPortedMemory; letiMem = mem.iport; letdMem = mem.dport; PipeReg#(FBundle) fr <- mkPipeReg; PipeReg#(WBBundle) wbr <- mkPipeReg; ruledoProc; BooliAcc = False; if(fr.notFull) begin let inst <- iMem(MemReq{op:Ld, addr:pc,data:?}); iAcc = True; fr.enq(FBundle{pc:pc, epoch:epoch, inst:inst}); end http://csg.csail.mit.edu/SNU

  4. Three-Stage SMIPS AddrredirPC = ?; BoolredirPCvalid = False; if(fr.notEmpty && wbr.notFull) begin letpc = fr.first.pc; let inst = fr.first.inst; if(fr.first.epoch==epoch) begin letdInst = decode(inst); Bool stall = wbr.notEmpty && wbr.first.rDstValid && ((dInst.rSrc1Valid && dInst.rSrc1==wbr.first.rDst) || (dInst.rSrc2Valid && dInst.rSrc2==wbr.first.rDst)); http://csg.csail.mit.edu/SNU

  5. Three-Stage SMIPS if(!stall) begin Data rVal1 = rf.rd1(dInst.rSrc1); Data rVal2 = rf.rd2(dInst.rSrc2); let eInst = exec(dInst, rVal1, rVal2, frpc); if(memType(eInst.iType)) eInst.data <- dMem(MemReq{ op: eInst.iType==Ld ? Ld : St, addr: eInst.addr, data: eInst.data}); if(eInst.brTaken) begin redirPC = eInst.addr; redirPCvalid = True; end wbr.enq(WBBundle{iType:eInst.iType, rDst:eInst.rDst, data:eInst.data}); fr.deq; end end http://csg.csail.mit.edu/SNU

  6. Three-Stage SMIPS else fr.deq; end if(wbr.notEmpty) begin if(regWriteType(wbr.first.iType)) rf.wr(wbr.first.rDst, wbr.first.data); wbr.deq; end pc <= redirPCvalid ? redirPC : iAcc ? pc + 4 : pc; epoch <= redirPCvalid ? !epoch : epoch; endrule endmodule http://csg.csail.mit.edu/SNU

  7. Five-Stage SMIPS Register File Epoch stall? PC Execute Decode wbr fr er dr +4 Data Memory Inst Memory http://csg.csail.mit.edu/SNU

  8. Five-Stage SMIPS modulemkProc(Proc); Reg#(Addr) pc <- mkRegU; Reg#(Bool) epoch <- mkRegU; RFilerf <- mkRFile; Memory mem <- mkTwoPortedMemory; letiMem = mem.iport; letdMem = mem.dport; PipeReg#(FBundle) fr <- mkPipeReg; PipeReg#(DBundle) dr <- mkPipeReg; PipeReg#(EBundle) er <- mkPipeReg; PipeReg#(WBBundle) wbr <- mkPipeReg; ruledoProc; BooliAcc = False; if(fr.notFull && iMem.notFull) begin iMem.req(MemReq{op:Ld, addr:pc, data:?}); iAcc = True; fr.enq(FBundle{pc:pc, epoch:epoch}); end http://csg.csail.mit.edu/SNU

  9. Five-Stage SMIPS if(fr.notEmpty && dr.notFull && iMem.notEmpty) begin let dInst = decode(iMem.resp); dr.enq(DBundle{pc:fr.first.pc, epoch:fr.first.epoch, dInst:dInst}); fr.deq; iMem.deq; end Addr redirPc = ?; Bool redirPCvalid = False; if(dr.notEmpty && er.notFull && (!memType(dr.first.dInst.iType) || dMem.notFull)) begin if(fr.first.epoch==epoch) begin let dInst = dr.first.dInst; Bool eStall = er.notEmpty && er.first.rDstValid && ((dInst.rSrc1Valid && dInst.rSrc1==er.first.rDst) || (dInst.rSrc2Valid && dInst.rSrc2==er.first.rDst)); http://csg.csail.mit.edu/SNU

  10. Five-Stage SMIPS Bool wbStall = wbr.notEmpty && wbr.first.rDstValid && ((dInst.rSrc1Valid && dInst.rSrc1==wbr.first.rDst) || (dInst.rSrc2Valid && dInst.rSrc2==wbr.first.rDst)); if(!eStall && !wbStall) begin Data rVal1 = rf.rd1(dInst.rSrc1); Data rVal2 = rf.rd2(dInst.rSrc2); let eInst = exec(dInst, rVal1, rVal2, dr.first.pc); if(memType(eInst.iType)) dMem.req(MemReq{op:eInst.iType==Ld ? Ld : St, addr:eInst.addr, data:eInst.data}); if(eInst.brTaken) begin redirPC = eInst.addr; redirPCvalid = True; end er.enq(EBundle{iType:eInst.iType, rDst:eInst.rDst, data:eInst.data}); dr.deq; end end else dr.deq; end http://csg.csail.mit.edu/SNU

  11. Five-Stage SMIPS if(er.notEmpty && wbr.notFull && (!memType(er.first.iType) || dMem.notEmpty)) begin wbr.enq(WBBundle{iType:er.first.iType, rDst:er.first.rDst, data:er.first.iType==Ld ? dMem.resp : er.first.data}); er.deq; if(dMem.notEmpty) dMem.deq; end http://csg.csail.mit.edu/SNU

  12. Five-Stage SMIPS if(wbr.notEmpty) begin if(regWriteType(wbr.first.iType)) rf.wr(wbr.first.rDst, wbr.first.data); wbr.deq; end pc <= redirPCvalid ? redirPC : iAcc ? pc + 4 : pc; epoch <= redirPCvalid ? !epoch : epoch; endrule endmodule http://csg.csail.mit.edu/SNU

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