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Mapping the FFT Algorithm to the IBM Cell Processor

This study explores the adaptation of the Fast Fourier Transform (FFT) algorithm for MRI imaging on the IBM Cell Processor, which features a powerful architecture with a Power Processing Unit (PPU) and eight Synergistic Processing Units (SPUs). We detail an efficient discrete Fourier transform (DFT) approach that includes 2D FFT implementation through row and column transformations. Our strategy addresses memory limitations through quad buffering, data striping, and optimized processing routines, highlighting the challenges faced during development, including compiler interactions and parallel processing techniques.

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Mapping the FFT Algorithm to the IBM Cell Processor

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  1. Mapping the FFT Algorithm to the IBM Cell Processor Andy Polidore Advisors: Brendan Burns, Joseph Czechowski

  2. Motivation • MRI Imaging • Fast Fourier Transformations • Efficient algorithm for computing a Discrete Fourier Transform • DFT converts time-domain to frequency-domain • 2D FFT: Perform a 1D FFT on each row of an image and then perform a 1D FFT on each resulting column • The Cell • Nine cores • 1 Power Processing Unit (PPU) • 8 Synergistic Processing Units (SPU)

  3. Strategy • Cell comes with 2d routine • Needs to be called twice • First call organizes the data in contiguous column form • Striping • Limited SPU memory • Quad Buffering

  4. PPU SPU 0 Input Buffer Input DMA In FFT Output Buffer FFT out DMA Out PPU SPU 0 Input Buffer Input DMA In FFT Output Buffer FFT out DMA Out

  5. SPU 0 PPU SPU 1 SPU 7 Input Buffer DMA In Input FFT Output Buffer FFT out

  6. PPU SPU 0 SPU 1 Input Buffer SPU 2 Input DMA In FFT Output Buffer FFT out DMA Out PPU Sync Point SPU 0 SPU 1 Input Buffer SPU 2 Input DMA In FFT Output Buffer FFT out DMA Out

  7. Quad buffering • Why it is required? • Space problems • Maximizing processing power • Buffers • IN to handle incoming data • FFTin and FFTout to process the data • OUT stores the data ready to be DMA’ed back to main memory

  8. Buffering A B C D 0 FILL ------- ------- ------- 1 2 3 4 5 6

  9. Buffering A B C D 0 FILL ------- ------- ------- 1 FFTOUT FILL ------- FFTIN 2 3 4 5 6

  10. Buffering A B C D 0 FILL ------- ------- ------- 1 FFTOUT FILL ------- FFTIN FFTOUT 2 OUT FFTIN FILL 3 4 5 6

  11. Buffering A B C D 0 FILL ------- ------- ------- 1 FFTOUT FILL ------- FFTIN FFTOUT 2 OUT FFTIN FILL 3 OUT FILL FFTOUT FFTIN 4 5 6

  12. Buffering A B C D 0 FILL ------- ------- ------- 1 FFTIN FFTOUT FILL ------- 2 FFTOUT OUT FFTIN FILL 3 OUT FILL FFTOUT FFTIN 4 FILL FFTIN OUT FFTOUT 5 FFTIN FFTOUT FILL OUT 6 FFTOUT OUT FFTIN FILL

  13. Striping Main Memory SPU 0 SPU 1 SPU 2 SPU 3 SPU 4 SPU 5 SPU 6 SPU 7

  14. Challenges • Simulator • Testing is slow • Alignment • Compiler • C coding • Working with bytes • Parallel processing • Data movement • Debugging

  15. Knowledge Gained • Mastering Linux • C make files, linking, etc • Data movement strategies • Multi-core processing • Debugging!

  16. Results and Conclusions • Success? • Future Work • Arbitrary size input

  17. Questions?

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