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Pei-Chen Chiu On-behalf of the TPS Feedback Team NSRRC, Hsinchu, Taiwan

Pei-Chen Chiu On-behalf of the TPS Feedback Team NSRRC, Hsinchu, Taiwan. Power Supply Control Interface and Orbit Feedback Environment for TPS. Outline. TPS Power Supply & Control Interface Integrated Orbit Feedback System Infrastructure Corrector Control Interface

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Pei-Chen Chiu On-behalf of the TPS Feedback Team NSRRC, Hsinchu, Taiwan

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  1. Pei-Chen Chiu On-behalf of the TPS Feedback Team NSRRC, Hsinchu, Taiwan Power Supply Control Interface and Orbit Feedback Environmentfor TPS

  2. Outline • TPS Power Supply & Control Interface • Integrated Orbit Feedback System Infrastructure • Corrector Control Interface • BPM & Feedback Engine Interface • Summary

  3. Power Supply and Control Interface

  4. Storage Ring Power Supply (1/2) Storage Ring Dipole PS Parameters Unipolar Type Maximum current 750 A Nominal voltage rating 850 V Current control range 25-750 A Current Stability (100 s to 8 hours)±10 ppm Award to IE Power Control Interface Ethernet (similar with CLS) Storage Ring Quadrupole PS Parameters Unipolar, switched-mode Maximum current rating 250 A Nominal voltage rating 30 V Current control range 20-250 A Current Stability (0 to 8 hours)±2.5 mA p-p Contracted to Chroma ATE Inc Control Interface Ethernet (LXI compatible)

  5. Storage Ring Power Supply (2/2) Storage Ring Sextupole PS Parameters (Include Transport line Magnet PS) Unipolar, switched-mode Maximum current rating 250 A Nominal voltage rating 30 V Current control range 20-250 A Current Stability (0 ~ 8 hours)±12.25 mA p-p Contracted to Chroma ATE Inc Control Interface Ethernet (LXI compatible)

  6. Booster Ring Power Supply Booster Dipole PS Parameters Quadrant operation (Voltage bipolar, current unipolar) Typical waveform 3Hz biased sine wave Maximum peak current 1200 A Nominal peak voltage(option1/2) + 1500 V Current control range 36-1200A Current Stability (100 s to 8 hours)±10 ppm Award to IE Power Control Interface Ethernet (similar as CLS) Booster Quadrupole PS Parameters Quadrant operation (Voltage bipolar, current unipolar) Typical waveform 3Hz biased sine wave Maximum peak current 120 A Nominal peak voltage(option1/2) + 425 V Current control range 1-120A Current Stability (100 s to 8 hours)±10 ppm Award to IE Power Control Interface Ethernet (similar as CLS)

  7. Storage Ring : Corrector, Skew Quad Power Supply Booster : Corrector, Sextupole Power Supply LTB, BTS : Corrector Power Supply Corrector & BR Sextupole PS Parameters Bipolar, switched-mode Maximum peak current ± 10 A Nominal peak voltage(option1/2) + 48 V Current control range -10~10A Noise level < 100 mA Current Stability (0 ~ 8 hours)± 100 mA p-p Manufactured by Industrial Technology Research Institute Control Interface Analogue interface Storage Ring Slow Corrector (± 600 mrad) noise level < 5 nard (< 10 ppm)

  8. Booster Main Power Supply Control Interface TPS Control Network EPICS IOC ADLINK cPCI CPU EPICS IOC ACQ164CPCI 24 bits ADC, 32 ch, GbE EVR (CPCI6U-EVR-300) ADLINK 128 Bits DI/DO Interlock PLC IOC TEWS TCP201 IP Carrier Hytec IP ADC 24 bits, 16 channels IP-ADC-8417 Hytec IP DAC 18 bits, 16 channels IP-DAC-8415 Ethernet Interface: On/Off control Status readback Interlock reset Trigger Fanout Ethernet Switch Ramp Trigger Sextupole SD, SF PS Trigger BR frev clock 3 Hz Power supplies trigger Booster Dipole, QF, Q1, Q2, QM PS (IE Power Inc.) Two Options: Analogue Reference Input (Waveform) or Embedded Waveform Generator

  9. SR Power Supply Control in one Cell TPS Control network Orbit Feedback Setting (10 kHz rate) Corrector Power Supply Controller (CPSC) Cell Power Supply Control cPCI IOC EPICS Access (10 Hz rate) CPU Module EVR (cPCI-EVR-300) EPICS IOC 20 bits DAC 24 bits ADC (D-Tacq) CLK/Trigger Ethernet Switch ±10 Amp Power Supplies (ITRI) Dipole PS (IE Power) x 1 Quad (10), Sextupole (7) (Chroma ATE Inc.) x 24 SR Slow Correctors 168 (H) +168 (V) SR Fast Correctors 96 (H) + 96 (V) Skew Quadrupole 96 BR Correctors 60 (H) + 36 (V)

  10. Integrated Orbit Feedback System Infrastructure

  11. CV/CH CV/CH CV/CH CV/ CH CV/CH CV/CH CV/CH TPS Slow and Fast Correctors for one Cell Boundary Conditions: Al Chamber (4 mm in thickness) 7 BPM/cell (more will add in future) 7 slow horizontal and 7 slow vertical corrector 4 fast horizontal and 4 fast vertical corrector Slow Correctors Fast Correctors

  12. BPM Arc BPM Straight BPM (Primary BPM) Racetrack chamber Courtesy by Vacuum Group

  13. Slow Correctors SR-SM (S2) Winding on sextupole magnets Horizontal 7 x 24 = 168 Vertical 7 x 24 = 168 SR-SM (S4) Fast Correctors SR-SM (S3) Horizontal 4 x 24 = 96 Vertical 4 x 24 = 96 Mount on Bellows to achieve required bandwidth. 13

  14. BPM electronic & IOFB module • Platform : Libera Brilliance+ • Feedback Engine implemented in IOFB module Grouping and IOFB module

  15. TPS Infrastructure for IOFB • SOFB at beginning, then FOFB later, running FOFB only! • SOFB and FOFB running as two independent system with frequency dead-band. FOFB run from DC, a slow system receives the fast correctors from their DC part to prevent saturation. SOFB + FOFB S O F B FOFB • Only FOFB FOFB FOFB • Orbit feedback system with combined fast and slow correctors IOFB Slow control rules Accelerator Response Slow corrector BPMs Fast control rules Accelerator Response Fast corrector Golden Orbit

  16. Required Elements for IOFB 7 x 24 BPM 7 x 24 slow horizontal corrector + 7 x 24 slow vertical corrector 4 x 24 fast horizontal corrector + 4 x 24 fast vertical corrector 2 x 24 IOFB modules (one for slow correction loop; one for fast correction loop) 3 x 24 CPSC modules (one for slow horizontal corrector interface; one for slow vertical corrector interface; one for fast horizontal and vertical corrector interface) Each cell (of 24 cells) should have 2 Brilliance+ platforms equipped with IOFB modules + 3 CPSC.

  17. Infrastructure TPS Control System Control Network Timing Master IOC BPM soft IOC Master Clock Path length compensation On-line modeling computer EPICS CA Related BPM Control Diagnostic IOC Cell 2 3 CPSCs+ PSs Power supply 10 kHz rate interface. Each cell has 2 links. One for slow hor. and ver. loop. One for fast hor. and ver. loop Cell 1 3 CPSC s+ PSs Cell 24 3 CPSCs+ PSs BPM Group 1 BPM Group 2 BPM Group 24 Group BPM Output TPS Ring BPM platform 1 IOFB module 1 BPM platform 1 IOFB module 1 BPM platform 1 IOFB module 1 BPM platform 2 IOFB module 2 BPM platform 2 IOFB module 2 BPM pltform2 IOFB module 2 Rocket I/O grouping link XBPM Electronics 1 XBPM Electronics 1 XBPM Electronics1 XBPM Electronics m XBPM Electronics n XBPM Electronics n

  18. Simulation Results Simulated noise sensitivity function of the corrector VC014to bpm BPM011. 3 dB B.W. ~ 500 Hz

  19. A Kick Change Simulation Results • Capability of OFB to suppress perturbation could be up to 20 dB for slower noise. • Corrections of fast correctors is almost less than plus/minus 0.05 urad at final, which is smaller than correction of slow correctors

  20. Corrector Control Interface

  21. Corrector Power Supply Interface • Analogue interface • Choose 20 bits DAC • Tested prototype • Remote DAC setting (DAC installed at cPCI crate) • Analogue sum (DC orbit correction + feedback compensation) • Difficult to achieve better than 17 bits performance. Thus, it decided to install the DAC/ADC as closed as power supply as possible. • DAC/ADC interface and PS put at the same crate.

  22. 10 hour test of 20bit DAC (AD5791) (Full range +/- 6.6V) 6 count

  23. Temperature Effect on DAC output 5 ℃change=> 80 uV drift 16 uV(~1count)/ ℃

  24. Linearity test Each step: 1 count (~12.6 uV) settings • 12.6 uV step change • σ=0.047 uV • (less than 0.01 count)

  25. D-TACQ 18 bits DAC Module Output Test at Equipment Area Measurement Comparison In the equipment site, it has more obvious power line noise. 1 count increasing

  26. D-TACQ AO32 18 bits DAC Module & 20 bits DAC Evaluation Module Output Comparison

  27. Use D-TACQ AO32 18 bits DAC Module Output as Reference Input of Power Supply Module (Two separated rack, through 12m cabling) When connect to power supply, due to power-ground isolation, long-cabling induced noised and etc., the performance is deteriorated. The -80 dB noisy level is much higher than acceptable -106 dB. 1 mA (~ 60 nard) 100 mA (~ 6 nard) 10 mA (~ 0.6 nard)

  28. 20bit DAC Setting Power Supply Test Insert into PS crate slot 0 First modules Second modules 1 mA (~ 60 nard) 100 mA 10 mA Reference 1 mA (~ 60 nrad) 100 mA 10 mA I monitor

  29. Corrector Power Supply (± 10 A) With Corrector magnet Load Current output Amplitude v.s. Frequency 29 29

  30. Corrector Power Supply Controller (CPSC) External Clock (Up to 10 kHz Fast Setting Clock) 4 ways, 8 ch adder 8 Ch, 20 bit DAC DO (LEMO connector, for timing measurement), Trigger out, Package received Fast Setting Ports (GbE, UDP/IP), Through Port Setting Buffers SFP Port Ethernet Interface (Hardware UDP Stack) Rx Tx Heartbeat Register Fast Setting Port, Through Port (AURORA) Rx AURORA + Tx Heartbeat Register Precise digital temperature sensors Trigger (3 Hz) Sequencer 10 kHz clock ~8 x 64 k x 32 bit Waveform Memory Slow Setting Buffer Slow Trigger (on demand, may not necessary) 96 pin DIN61412 Connectors x 2 Control and Status Registers Individual Channel Enable/Disable? 8 ch, 24 bit ADC (10 kHz Sampling) Slow Access (~ 10 Hz) 10 kHz rate waveform Waveform Memory Single Board Computer (Linux, EPICS IOC) 10 Hz rate data Gigabit Ethernet 24 ch, 16 bit ADC Slow Access (~ 10 Hz) Control and Status Registers Status Registers 8 bit DI +/- 15 V + 5 V Write Registers 8 bit DO

  31. Block Diagram of CPSC IOFB correction ID fast compensation

  32. Feedback Engine Interface

  33. Requirement for IOFB modules • Data Concentration of BPM data (X, Y, Sum, Status/Counter) and support up to 256 BPM/pBPM. (utilize SFP1 & SFP2) • Configurable 2 SFP output. (utilize SFP3 & SFP4) • Output of grouped BPM/pBPM data via UDP/IP over GbE or customized AURORA protocol. • Output of grouped magnet correction data via UDP/IP over GbE or customized AURORA protocol. • Both of AURORA/GbE and BPM/magnet correction could be configured. • Inverse Response Matrix Calculation • Inverse matrix coefficient could be set by EPICS CA. • Corresponding magnet ID according to matrix could also be set by EPICS CA. • Golden orbit set by EPICS CA too. • PI controller for different eigen-modes. • 20 tap FIR. • Trigger mechanism

  34. Infrastructure of IOFB modules LVDS RX form 4*RAFs Grouping SFP1 4*BPM data SFP2 Output Mapping? ??? Orbit Data (168 BPM, X and Y) LVDS TX to TIM custom out - SFP3 Golden Orbit (X and Y) + Magnet/BPM AURORA/GbE 20 tap filters Output Mapping? n*PID controllers dp DM(m*1) = R-1 * Dp (n*1) SFP4 Magnet/BPM AURORA/GbE On/Off

  35. Interconnection within Cell’s CIA To Cell N-1 Group 14*Magnet output CPSC for slow horizontal corrector 7 repeater CPSC for slow vertical corrector 7 Reserve for future expansion ( such as pBPM input?) Group 8*Magnet output CPSC for fast horizontal and vertical corrector 4 + 4 Group 168*BPM output For diagnostic To Cell N+1

  36. IOFB algorithm (1/2) • There are total 4 response matrix: sRx,sRy,fRx,fRy. • These four matrix will be decomposed by SVD. For example, Slow horizontal response matrix 𝚼x=uxΣxvxT • Therefore, inverse response 𝚼x-1=vxΣx-1uxT • In order to do model space calculation, it is recommended that the IOFB modules should be allowed to download off-line the respective three elements: vx , Σ x-1 , uxT • Where uxT is 168*168 matirx(168 BPM), , Σ x-1 is 168(or less than 168) array, and vx is also 168*168 matirx • Since the IOFB is a kind of the distributed system, the calculation is also distributed. For example, for the 7 slow horizontal correction of the first cell. It is calculated as,

  37. IOFB algorithm (2/2) • Since TPS has 168 BPM and 168 slow correctors, there are 168 mode for slow loop in IOFB calculation and 96 mode for fast loop. • For the 4 fast horizontal correction of the first cell. It is calculated as, • The slow and fast loop would be calculate in two separate IOFB modules. • For slow loop, it should know Ux(168*168) and Uy(168*168), Sx, Sy(each mode weights), 168 mode PID coefficient, and submatrix of Vx(7*168), Vy(7*168) • For slow loop, it should know the first 96 mode of ux(96*168) and uy(96*168), sx, sy(each mode weights), 96 mode PID coefficient, and submatrix of vx(4*96), vy(4*96).

  38. Block diagram Reference Orbit IOFB coefficient + UT V Corrector PID*S-1 - Slow:168 Fast: 96 Slow loop:168*168 Fast loop:96*168 Slow:168*168 Fast: 96*96 Response Matrix R = U* S * VT Accelerator Vacuum Chamber BPM + Measured Orbit + Measured Noise Orbit Disturbance due to various sources Orbit

  39. Different size of response matrix calculation For the fast loop of the first cell, the IOFB should have 4 vertical fast magnet and 4 horizontal fast magnet . For the slow loop of the first cell, the IOFB should have 7 vertical fast magnet and 7 horizontal fast magnet. Support sizable matrix calculation or fixed to maximum configuration (unused part padded with zero). = m n

  40. BPM ID & Magnet ID • BPM ID: 1~168 • Magnet ID: • Beside IOFB, the global application is also considered. Ex, corrector response measurement, insertion device compensation. • Therefore, distinct Magnet ID is required for all correctors • 168*2+96*2=528 • According to response matrix, output should be ordered and assigned a magnet ID. • Magnet ID number is depended on the, classified, location and order. Such as, Horizontal fast corrector 23th cell Magnet ID Format 3rd corrector

  41. Summary • Overview of TPS power supply control • Feedback system infrastructure. • BPM and corrector interface. • Corrector power supply controller (CPSC) were contracted to D-Tacq. • I-Tech award the contract of BPM platforms. • Specifications for integrated orbit feedback (IOFB) FPGA modules are still on going. • Communication between CPSC and IOFB modules are in proceed now.

  42. Thanks for Your Attention!

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