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Introduction to the von Neumann Model of Computer

This overview provides an introduction to the von Neumann model of computer, its components, and organization. It explains the role of memory, CPU, control unit, and I/O devices and how they interact through the system bus. An example organization, the LC-3 computer, is also discussed along with its instruction formats and data paths.

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Introduction to the von Neumann Model of Computer

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  1. Overview von Neumann Model Components of a Computer Some Computer Organization Models The Computer Bus An Example Organization: The LC-3

  2. The von Neumann Model The Instruction is the smallest piece of work specified in a program The program cannot do just a piece of an instruction The Computer consists of 5 parts: Processing unit (CPU) Memory Input Output Control Unit The computer program is contained in memory with the data in the memory, they are indistinguishable

  3. Basic Computer Components

  4. Memory • Computer memories are characterized by - The number of locations: 2m Each location is identified by an address • The number of bits in a location: n Each location can contain data of computer instructions • “partitions” of the memory are restricted to use for: • Operating System • User program(s) • Input & Output (I/O) addresses (“mapped” I/O) • Alternatively, I/O can have a separate set of addresses • Etc.

  5. Computer Main Memory

  6. CPU • The CPU has to be able to perform operations, e.g. • Read from memory • Write to memory • Decode Instructions • Compute (Arithmetic, Logic, ..) • Etc. • The CPU will have temporary storage: • Registers to store data temporarily • A register to hold the Instruction being executed • A register to point to the next instruction to be executed • A register to hold the present status of the active program • Etc.

  7. Expanded Basic Computer Components

  8. Control Unit • The control unit is a finite state machine that controls the operation of the computer • Controls reading from memory • Controls writing to memory • Decodes instructions • Controls the execution of instructions • Controls I/O reads and writes • Controls the operation and timing of the System Bus • Etc.

  9. I/O Devices • I/O devices are external to the computer and connected through “interfaces”: • They provide data buffering • They provide control of the I/O devices • They provide for communication with the computer

  10. System Bus • The System Bus provides a conduit for transfer on data between: • The Memory • The I/O Device Interfaces • The CPU • The System Bus is composed of: • Data Lines • Address Lines • Control Lines

  11. System Bus Virtually all of the communication between the computer components, e.g. movement of instructions and data, is conducted over the System Bus

  12. Example Computer Organization

  13. LC-3 Computer Overview The LC-3 Computer 16 bit machine, word addressable, 64K or 65,536 locations Computer Machine Instructions – Computer “native” instructions The basic instructions that all programs use on that computer (The “atomic” unit of work done by a computer – see next slide) The Architecture (Organization) The hardware (state machine) that executes the instructions The Memory Holds the Operating System, the Program, support routines, data, .. The Instruction Cycle The steps in the execution of an instruction (machine language)

  14. The Instruction Cycle • Steps (or phases or states): • FetchNext Instruction from Memory • (PC)  (points to) next instruction • PC (PC) + 1 • Decode Fetched Instruction • EvaluateAddress (es) (find where the data is) • FetchOperand (s) (get data) • ExecuteOperation • StoreResult (if specified)

  15. Computer Machine Instruction Formats • What is IN an instruction? • Operation code– what to do • Input Operand(s)– where to get input operands (memory, registers) • Output Operand(s)– Where to put results (memory, registers) • What are the major instruction types? • Data Movement (load, store, etc.) • Operate (add, sub, mult, OR, AND, etc.) • Control (branch, jump to subroutine, etc.)

  16. What does an Instruction look like ? • One Address Instruction: • Format: Op code + Address • The operation is performed on the Operand addressed and likely the value in an accumulator register in the CPU and likely places the result in the accumulator • Two Address Instruction: • Format: Op code + Address + Address • The operation is performed on the 2 Operands addressed and places the result in one of the Operand Addresses • Three Address Instruction: • Format: Op code + Address + Address + Address • The Operation is performed on two operand identified by two of the addresses and places the result where the third address specifies

  17. More of Instruction Formats • The Instruction contains the opcode and the operands or operand addresses • Instructions are often limited to one word length • If so, the opcode and all operands/addresses must fit in one word. • Depending on the word length, this can severely limit the instruction format.

  18. LC-3 Instructions (Fig 5.3 – Appendix a) Memory Move Instructions: LD, LDI, LDR ST, STI, STR LEA Arithmetic/Logic Instructions: ADD, AND, NOT Transfer/Control Instructions: BR, JMP TRAP, JSR, JSRR RET, RTI

  19. Data Paths of the LC-3

  20. Important Registers in the CPU • 8 General Purpose Registers – Holds Data/Addresses • PC – Points to the next instruction to be executed • IR – holds the instruction being executed • PSW (includes NZP) – holds the status of the program being executed • MAR – Holds the address of the memory location being accessed • MDR – Hold the data to be written into memory or the date read from memory

  21. Components of the LC-3 CPU Combinational Logic Storage State Machine

  22. LC-3 Memory Layout • MAIN MEMORY: • x0000 – x2FFFSystem: Operating System programs, tables, • and data - Generally off limits to programmer • (Programs run in Supervisor mode) • x3000 – xFDFFUser: User Program and Data Area • Area shared by users like you • (Nominally run in non-supervisor mode) • xFE00 – xFFFFDevice: I/O Register Addresses • Pseudo memory used for input/output • CPU MEMORY: • R0-R7 Registers (16 bit)

  23. LC-3 Memory Map

  24. The LC-3 Instruction Addressing Modes • Register (Operand is in one of the 8 registers) • Immediate (Operand is in the instruction) • PC-relative (Operand is “offset” from the (PC) ) • Indirect (The “Operand” actually points to the real address of the • Operand – rather than being the operand) • Base + Offset (Base relative) (Operand is “offset” from the • contents of a register) • Note: NO Direct Addressing is defined in the LC-3 • Direct Addressing (“Operand” is the address of the Operand)

  25. The LC-3 Computeravon Neumannmachine • The Instruction Cycle • Fetch: Next Instruction from Memory • (PC)  (points to) next instruction • PC (PC) + 1 • Decode: Fetched Instruction • Evaluate: Instr &Address (es) • (find where the data is) • Fetch: Operand (s) • (get data as specified) • Execute: Operation • Store: Result • (if specified) PSW Memory PSW (Program Status Word): Bits: 15 10 9 8 2 1 0 | S| |Priority| | N| Z| P|

  26. LC-3 Instructions (Fig 5.3 – Appendix a) • Addressing Modes • Register • (Operand is in one of the 8 registers) • PC-relative • (Operand is “offset” from where the PC points) • Base + Offset (Base relative) • (Operand is “offset” from the contents of a register) • Immediate • (Operand is in the instruction) • Indirect • (The “Operand” points to the real address of Operand • – rather than being the operand)

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