1 / 22

Multicast Parallel Pipeline Router Architecture for Network-on-Chip

About this paper. Present a flexible mesh router architecture supporting unicast and multicast serviceA flexible mechanism to manage broadcast flow. Introduction . By the end of this decade, the transistor feature size will be 50-nm and it operates below one volt. requirements and should be scala

della
Télécharger la présentation

Multicast Parallel Pipeline Router Architecture for Network-on-Chip

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

    1. Multicast Parallel Pipeline Router Architecture for Network-on-Chip Author: Faizal A. Samman, Thomas Hollstein, Manfred Glesner, Speaker: ??? DATE,2008

    2. About this paper Present a flexible mesh router architecture supporting unicast and multicast service A flexible mechanism to manage broadcast flow

    3. Introduction By the end of this decade, the transistor feature size will be 50-nm and it operates below one volt. requirements and should be scalable for wide range. (ITRS) SoCs will grow to 4-billion transistors running at 10 GHz. A limiting factor for the performance, and energy consumption will be on-chip physical interconnections

    4. Introduction Networks-on-Chip provide advanced intellectual properties IP communication concepts for SoCs Sharing the wires between several communication flows makes the use of the wires more efficient

    5. Traditional 4X4 mesh NOC topology

    6. NoC design principle The architecture and routing decision must meet bandwidth requirements and should be scalable for wide range of applications For example : Network topology could influence the scalability and performance

    7. Synchronous /Asynchronous design Synchronous Extra clock power consumption electromagnetic interference effect Asynchronous A promising concept lacks of industrial standard support, especially with respect to testability issues

    8. General router architecture for XHiNoC Port FIFO Routing engine ID manager Link state controller

    9. Packet format Using 3 bits to record packet type (header ,body ,tail); Using 3 bits to record local id number to differentiate it from another

    10. Multicast procedure Forwarding Header Flits A header flit by a header flit Record the direction based on its ID in registers Broadcasting Payload Flits Each time a flit appears in the FIFO output, the LUT (look up table ) will check its ID to find its directions in the routing table

    11. ID-tag-basedMulticast Routing Two issues Packet flows are controlled based on ID-tags All flits of a packet have the same ID-tag on a certain communication link

    12. ID-tag-basedMulticast Routing If the target directions are more than one, the flit will be broadcasted in parallel.If the target directions are more than one, the flit will be broadcasted in parallel.

    13. Packet Identity Management IDM IDM Update new ID for new packet flowing through the outport. Guarantee that different packets will have a different ID-tag. Stop forwarding when IDs is run out. Delete all information about a certain ID when the tail flit flows through IDM Paper??? VC size?8?flit?? ???????id ?3bit?? each port haveaIDM !!!!!! ??in order delivery of a packet when using adaptive routing algorithmPaper??? VC size?8?flit?? ???????id ?3bit?? each port haveaIDM !!!!!! ??in order delivery of a packet when using adaptive routing algorithm

    14. Synchronous Parallel Pipelined Switching

    15. Synchronous Parallel Pipelined Switching 1st cycle: RE sends direction request signals to the LCFS 2nd cycle: The arbiter in the LCFS has selected the winner to access the outport by sending a grant

    16. Multicast Broadcast-flow Management LCFS(Link Controller and Flow supervisor) Three major part DecMC unit decodes 3-bit routing direction request signals from all inports into 1-bit signals. arbiter is in charge of selecting a winner of all the requests GMC is in charge of granting the FIFO

    17. Multicast Broadcast-flow Management

    18. Multicast Broadcast-flow Management Why forwarding For instance : When one of the direction is not win the arbitraction Using forwarding could reset the successful way: to avoid the flit being forwarded more than once into the same outport

    19. Broadcast-FlowManagement

    20. Experiment Results Experiment setting injecting 2 multicast packets,which have 7 destinations in 2-D 4x4 mesh topology. Each packet consists of 128 flits,it means, that each packet header is followed by 121 payload flits Traffic scenarios

    21. Experiment Results

    22. Experiment Results By using UMC 180nm standard-cell technology The XHiNoC can be run at 230 MHz. Total number of logic cells is 10577. Migrating from unicast to multicast with The same XY routing algorithm increases 15% of total logic cells using unicast service (9201 logic cells). Five FIFO buffers occupy 44% of total cell area

    23. Conclusion and future work Propose a new mechanism to serve multicast packet For future works Adaptive routing algorithms

More Related