Computer Systems and Device Management

1. Computer Systems and Device Management Fred Kuhns fredk@cse.wustl.edu Applied Research Laboratory, Department of Computer Science and Engineering, Washington University in St. Louis

2. Operating System File Manager Process & Resource Manager Memory Manager Device Manager Processor(s) Main Memory Devices Hardware OS Organization CS422 – Operating Systems Concepts

3. OS Techniques • Controlling access to hardware resources is done using hardware supported privilege levels, typically two: user and system • Privileged operations, resource management, protection enforcement (isolation), and sharing performed by a trusted control program: the Kernel • Users request OS services using a well defined interface that validates user and notifies OS of request: two common methods: • System calls: trap changes mode and executes privileged code in context of calling process • Message passing: interface constructs message and sends to another system (i.e. privileged) process CS422 – Operating Systems Concepts

4. char block Device drivers System Call – Traditional Monolithic Kernel execution environment application trap libraries user System call interface kernel System Services File subsystem dispatcher IPC Process control subsystem Buffercache Scheduler Exceptions Interrupt Memory hardware CS422 – Operating Systems Concepts

5. DB server Memory mngr Task mngr I/O mngr Message Passing – Micro-Kernel Client microkernel CS422 – Operating Systems Concepts

6. Arithmetic-Logical Unit (ALU) Control Unit Primary Memory Device Controller Device Device Controller Device Device Controller Device Device Controller Device Von Neumann Architecture Central Processing Unit (CPU) CS422 – Operating Systems Concepts

7. An Example: Port Processors for an IP Router ControlProcessor Switch Fabric ATM Switch Core IPP OPP IPP OPP IPP OPP IPP OPP IPP OPP IPP OPP FPX FPX FPX FPX FPX FPX Port Processors SPC SPC SPC SPC SPC SPC LC LC LC LC LC LC Line Cards (link interfaces) CS422 – Operating Systems Concepts

8. Dist. Q. Ctl. Dist. Q. Ctl. Dist. Q. Ctl. Dist. Q. Ctl. FlowLookup FlowLookup Flow/RouteLookup Flow/RouteLookup Functional Diagram of the Port Processor (SPC) ControlProcessor Switch Fabric SPC SPC OutputPortProc. InputPortProc. . . . CS422 – Operating Systems Concepts

9. The Smart Port Card: an embedded processor Switch Interface DRAM Link Interface CPU Module APIC PCI Bus System FPGA Serial Ports CS422 – Operating Systems Concepts

10. Typical Pentium PC Architecture Addr/Data Ctrl Ctrl Cache CPU North- Bridge DRAM Addr/Data/Ctrl PCI Bus Intr NMI INIT SouthBridge (PIIX3) (PIC, PIT, …) PCI Devices ISA Bus ISA Devices Super-IO BIOS BIOS RTC Uarts Kbd/Mse Floppy Parallel ... CS422 – Operating Systems Concepts

11. . . . . . . . . . Zooming in on Computer Architecture CPU Memory 0 1 PC MAR IR Reg N Instruction MBR Reg 1 Reg 0 Instruction I/O AR Instruction execution unit I/O BR Data Devices Data Data Data . . Buffers N PC - Program Counter IR - Instruction Register MAR - Memory Address Register MBR - Memory Buffer Register I/O AR - Input/Output Address Register I/O BE - Input/Output Buffer Register CS422 – Operating Systems Concepts

12. Processor Registers • User-visible registers • Enable programmer to minimize main-memory references by optimizing register use • Control and status registers • Used by processor to control operation of the processor • Used by operating-system routines to control the execution of programs CS422 – Operating Systems Concepts

13. User-Visible Registers • May be referenced by machine language • Available to all programs - application programs and system programs • Types of registers • Data - can be assigned by the programmer • Address - contain main memory address of data and instructions. Or may contain a portion of an address that is used to calculate the complete address. • Condition Code or flags CS422 – Operating Systems Concepts

14. Control and Status Registers • Program Counter (PC) • Contains the address of an instruction to be fetched • Instruction Register (IR) • Contains the instruction most recently fetched • Program Status Word (PSW) • condition codes • Interrupt enable/disable • Supervisor/user mode CS422 – Operating Systems Concepts

15. Fetch Cycle Execute Cycle Fetch Next Instruction Execute Instruction HALT START Instruction Cycle • Processor fetches instruction from memory • PC contains address of next instruction to be fetched • PC incremented after each fetch CS422 – Operating Systems Concepts

16. Modern Instruction Cycle • (a) A three-stage pipeline • (b) A superscalar CPU (Stallings, Operating Systems, 4th Edition) CS422 – Operating Systems Concepts

17. CPU Registers Memory Memory Memory Memory Memory Memory PC 300 AC IR 1940 300 300 300 300 300 300 1 9 4 0 1 9 4 0 1 9 4 0 1 9 4 0 1 9 4 0 1 9 4 0 301 301 301 301 301 301 5 9 4 1 5 9 4 1 5 9 4 1 5 9 4 1 5 9 4 1 5 9 4 1 302 302 302 302 302 302 2 9 4 1 2 9 4 1 2 9 4 1 2 9 4 1 2 9 4 1 2 9 4 1 0 0 0 3 0 0 0 3 0 0 0 3 0 0 0 3 0 0 0 3 0 0 0 3 940 940 940 940 940 940 941 941 941 941 941 941 0 0 0 2 0 0 0 2 0 0 0 2 0 0 0 2 0 0 0 2 0 0 0 5 Example of Program Execution CPU Registers PC 301 AC 0003 IR 1940 1 - load Step 1 Step 2 CPU Registers CPU Registers PC 301 PC 302 AC 0003 AC 0005 IR 5941 IR 5941 3 + 2 = 5 Step 3 Step 4 5 - add CPU Registers CPU Registers PC 302 PC 303 AC 0005 AC 0005 IR 2941 IR 2941 2 - store Step 5 Step 6 CS422 – Operating Systems Concepts

18. clock handler Interrupts – devices notify CPU of some event Processor Device table dispatcher (interrupt handler) X Bus command status rt-counter Timer Interrupt is generated every 10ms, used by OS for accounting and resource (CPU) sharing. CS422 – Operating Systems Concepts

19. Instruction Cycle with Interrupts Fetch Cycle Execute Cycle Interrupt Cycle Interrupts Disabled Check for & Process Int Fetch Next Instruction Execute Instruction START Interrupts Enabled HALT CS422 – Operating Systems Concepts

20. Interrupt Cycle • Processor checks for interrupts • If no interrupts fetch the next instruction for the current program • If an interrupt is pending • save current PC value • set PC to start of dispatcher • System interrupt dispatcher saves some general purpose registers, determines interrupt type (or id) and calls handler by indexing into an array of function pointers. CS422 – Operating Systems Concepts

21. Simple Interrupt Processing Hardware Software Device controller or other system hardware issues an interrupt Save remainder of process state information Processor finishes execution of current instruction Process interrupt Processor signals acknowledgment of interrupt Restore process state information Processor pushes PSW and PC onto control stack Restore old PSW and PC Processor loads new PC value based on interrupt CS422 – Operating Systems Concepts

22. What about Multiple Interrupts Simple Approach - disable interrupts • Use Priorities to differentiate between interrupt classes, run the highest priority pending interrupt. • Disable interrupts so processor can complete task • Interrupts remain pending until the processor enables interrupts • After interrupt handler routine completes, the processor checks for additional interrupts CS422 – Operating Systems Concepts

23. Device Driver I/O and Devices Processor Device table dispatcher (interrupt handler) X Bus command status data 0 data 1 Device Controller (firmware and logic) ... data N-1 Device X CS422 – Operating Systems Concepts