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All-Optical Header Processing in Optical Packet-Switched Networks

All-Optical Header Processing in Optical Packet-Switched Networks

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All-Optical Header Processing in Optical Packet-Switched Networks

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  1. All-Optical Header Processingin Optical Packet-Switched Networks Hoa Le Minh, Fary Z Ghassemlooy and Wai Pang Ng Optical Communications Research Group Northumbria Communications Research Lab Northumbria University U.K. July, 2005

  2. Contents • Overview of processing in optical networks • New Node Architecture • Proposed processing scheme • Results • Summary

  3. [bit/s] 1P 100T 10T 1T 100G 10G 1G 100M Total Data Voice 1995 2000 2005 2010 Optical Communications Traffic demand forecast (NEC–2001) Capacity increase : 2~4 times a year Bit cost decrease : 1/2 time a year • 1st generation optical networks: packet routing and switching are mainly carried out using high-speed electronic devices. • However, as the transmission rate continues to increase, electronically processing data potentially becomes a bottleneck at an intermediate node along the network. • Solution: All-Optical processing

  4. Future Optical Networks Source: NEC-2001

  5. PL H Edge Router Edge Router Edge Router Edge Router Edge Router Edge Router All-Optical Packet-Switched Networks(Core network) Core Network Optical transparent !

  6. P1 P2 P3 O/E Processing E/O PL H H A_99 … Routing table for a network with 128 nodes All-Optical Packet-Switched Networks 23 5 10 2 3 8 9 45 13 6 • All electronic node: • O/E & E/O conversions  limit processing speed • All-Optical node: • A large routing table – opt. memory issue • Complexity

  7. Electronic Processing Vs. Optical Processing

  8. All-Optical Processing -Proposed Approach Offers • Novel routing table in pulse-position modulation format • Small and fixed number of routing table entries regardless of the number of nodes in network. • High scalability • Using simple optical configuration (SMZI). • Ultrahigh speed and high capability • Header address matching is done readily with reduced size routing table.

  9. PL PL PL H H H Clk Clk Clk Proposed Header Processing Unit Port 1 All-Optical Switch Data packet Port 2 … Delay fiber Port M Optical Header Processor H Header Extraction PPM Conversion Control port 2 Control port M Control port 1 C[M] PPRT Control Synchronization Pattern of port 1 … Optical AND gate 1 Clk Clock Extraction Pattern of port 2 Optical AND gate 2 Matching pulse (Synchronized) … … Pattern of port M Optical AND gate M

  10. 1 0 1 1 0 … Data Packet Format Payload Header Sync Others Address Controls Parity … N bits (N optical pulses) • Data packet: • Optical pulses in RZ-format, • Speed a few hundreds Gbit/s • - Each bit slot spreads from dozens to a few picoseconds

  11. a3a2a1a0 LSB Tb 0 1 1 0 1 0 0 1 RZ Data Tsym Tsym Ts PPM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tb – bit duration, Ts – slot duration Pulse Position Modulation Format In PPM M-bit address symbol is converted into 2M-slot symbol

  12. 20Ts 21Ts 22Ts 23Ts x(t) y(t) SW1 SW2 SW3 SW4 a1 a2 a3 a0 Header Ext. Unit PPM Generation Optical Circuit N-bit address-codeword: A = [ai {0,1}], i = 0, …, N PP-format address: y(t) = x(t + ai2iTs)

  13. ith … … … … 0 1 2 3 4 2N-1 … … 0 1 2 3 4 2N-1 0 1 2 3 4 2N-1 PPM Based Routing Table M = 3 2N entries Processing gain: 2N- entry RT  M- entry PPM routing table M is fixed  number of entries is fixed at each node

  14. PPM Based Routing Table – contd. • Is initialized with the clock synchronization . M entries are filled by: • Single optical pulse + Array of 2N optical delay lines; Or, • M pattern generators + M optical modulators.

  15. SOA B A.B SOA1 B A A A.B SOA2 Ultrafast Optical AND Gate Implementation: - Using optical interferometer configuration Symmetric Mach-Zehnder Interferometer (SMZI) Terahertz Optical Asymmetric Demultiplexer (TOAD)

  16. All-Optical Switch C[1] 1 M 1 SMZI-1 C[2] 2 SMZI-2 … C[M] M SMZI-M Using an array of SMZI with controls provided from the processing unit

  17. Simulation Parameters ParametersValue Data bitrate 50Gbits/s Data packet length 53 bytes (424 bits) Data packet guard time 3 ns Header length 4 bits Data power (per pulse) 2mW Data pulse width (FWHM) 1 ps PPM slot Ts 5 ps Wavelength 1554 nm

  18. Simulation Results Incoming packet Extracted clocks

  19. Switched Outputs Node 1 Node 2 Node 3

  20. Summary • A novel node architecture encooprating all optical processing with much reduced routing table entries based om PPM was proposed and simulated using VPI simulation package. • It is possible to significantly increase the number of nodes in network as well as enlarge the size or routing table at each node without introducing large processing delay.

  21. Acknowledgements • One of the authors Hoa Le Minh is sponsored by the Northumbria University for his PhD study.

  22. Thank you!