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Basic Building Blocks

+. Basic Building Blocks. Adder. Multiplexer. Demultiplexer. The Program Counter. There is a special register inside the processor. Big enough to hold an instruction address (32 bits) . Called the program counter (PC). Zero ext. Branch logic. 0. A. ALU. 4. B. +. 31. +.

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Basic Building Blocks

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  1. + Basic Building Blocks Adder Multiplexer Demultiplexer

  2. The Program Counter • There is a special register inside the processor. • Big enough to hold an instruction address (32 bits). • Called the program counter (PC).

  3. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  4. Fetch - Execute • Fetch: • Send the value in the PC to the instruction memory. • The instruction memory gives out one instruction. • Execute: • Carry out the fetched instruction. • Also: PC := PC+4; Fetch Execute  108 times per second

  5. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  6. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  7. The Register File • 32 word (32 bit) registers. • r0 is special: • Read: always zero. • Write: allowed, but won´t change it. • r31 is special: • Hard-wired return address (lab1).

  8. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  9. Add Instructions • 32 bit operands. • Example: • Add rd rs rt. • rd := rs + rt. • There is also: • Addurd rs rt. • These are not add signed and add unsigned. The “u”-variant ignores overflow. 6 5 5 5 Opcode rs rt rd

  10. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Add rdrsrt

  11. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Add rd rs rt

  12. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Add rd rs rt

  13. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Add rd rs rt

  14. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Add rd rs rt

  15. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Add rd rs rt … next instr

  16. Sub Instructions • 32 bit operands. • Example: • Subrd rs rt • rd := rs - rt • There is also: • Suburd rs rt • These are notsub signed and sub unsigned The “u”-variant ignores overflow

  17. How to Negate • Y := -X? • Sub rd $0 rt ($0 means r0) • rd := 0 - rt • Careful: Neg  Not

  18. Compare Instructions • Signed integers: • Sltrd rs rt • if rs < rt then rd := 1else rd := 0 • Unsigned integers: • Sltu rd rs rt • if rs < rt then rd := 1else rd := 0

  19. Immediate Variants of the arithmetic instructions: • Addi rt rs Imm • Addiu rt rs Imm • Slti rt rs Imm • Sltiu rt rs Imm • Imm sign-extend • No sub instruction

  20. Sign/Zero extension • The immediate field is 16 bits • But most operations work on 32 bits! Zero extension Sign extension Immediate 0000000000000000 Immediate xxxxxxxxxxxxxxxx x Immediate 31 16 15 0 31 16 15 0 Bit 15, the Sign bit, is copied into bits 16 - 31

  21. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend

  22. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Addi rt rs Imm

  23. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Addi rt rs Imm

  24. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Addi rt rs Imm

  25. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Addi rt rs Imm

  26. Zeroext. Branch logic 0 A ALU 4 B + 31 + Sgn/Ze extend Addi rt rs Imm … next instr

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