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Noise and Reliability in Advanced Bipolar Technologies

Noise and Reliability in Advanced Bipolar Technologies. Md Mazhar Ul Hoque Advisor: Prof. Zeynep Celik-Butler Department of Electrical Engineering University of Texas at Arlington. Outline. Introduction: Limitations in existing noise models. Importance and motivation of research.

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Noise and Reliability in Advanced Bipolar Technologies

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  1. Noise and Reliability in Advanced Bipolar Technologies Md Mazhar Ul Hoque Advisor: Prof. Zeynep Celik-Butler Department of Electrical Engineering University of Texas at Arlington

  2. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  3. Current BJT low-frequency noise models • Gummel-Poon: • VBIC – Flicker noise due to IBE, IBEP • MEXTRAM: • MODELLA:

  4. Importance and motivation Limitations in existing noise models: • Only one single noise source in base current: SIB=KF.IBAF. • Noise in base current dominant only for higher base series resistance. • Does not include any geometry, temperature or process parameter. • Noise in collector current and internal resistances are neglected. • Noise in collector current contributes at lower base series resistance. • Noise from internal resistance contributes at higher bias current. • To model all possible noise sources in advanced bipolar transistors: • Noise in base current, collector current and internal resistances. • Developing physics based scalable equations for the noise sources: • Incorporating geometry, temperature and process dependant parameters. • Writing computer source code for device and circuit analysis CAD tools to incorporate all possible noise sources in BJT. Research goal:

  5. Advanced bipolar technologies under investigation • Polysilicon emitter bipolar transistors: • 2nd generation BiCMOS technology, Texas Instruments Inc. • NPN and PNP transistors. • Variable size, variable IFO thickness. • SiGe heterojunction bipolar transistors: • 1st generation BiCMOS technology, National Semiconductor Corporation. • NPN transistors. • Variable size, variable design rules. • Variable doping in base and collector.

  6. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  7. 12V (a) (b) RL RS 4.8V 100K 100K Collector-base measurement setup

  8. Collector-base measurement for unity coherence: If has the dominant contribution, If has the dominant contribution, If has the dominant contribution,

  9. Dominant noise source 0.7x100 μm2 NPN, thickest IFO, RS=1MΩ 0.7x100 μm2 PNP, thickest IFO, RS=1MΩ • Calculated SVC/SVB considering SIB contribution dominant closely matches experimental SVC/SVB; SIB contribution dominant.

  10. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  11. Area dependence of SIB in NPN transistors Noise source homogeneously distributed underneath the emitter. [ Darby Lan ]

  12. Internal emitter resistance and ideality factor of base current 0.7x100 μm2 NPN, thickest IFO, RS=1MΩ m gmi (ohm-1)

  13. Physical origin of SIB • Base current dependence • diffusion fluctuation in emitter. • tunneling fluctuation in IFO. • recombination fluctuation in emitter- base space charge region. recombination fluctuation at spacer oxide interface. • Emitter perimeter dependence • Noise source distributed homogeneously around the emitter. • Recombination fluctuation at the spacer oxide interface. • Emitter area dependence • Noise source distributed homogeneously underneath the emitter. • Diffusion fluctuation in emitter or tunneling fluctuation in IFO.

  14. Physical origin of SIB (cont.) • Unity ideality factor of negligible . negligible .

  15. Diffusion and tunneling fluctuation component of SIB 0.7x100 μm2 NPN, medium IFO, RS=1MΩ

  16. Area dependence of tunneling fluctuation of SIB in PNP transistors Thickest oxide Tunneling-fluctuation source homogeneously distributed underneath the emitter. Smaller device-dimension severely affected by lateral diffusion and mask undercut; effective emitter area considered.

  17. αm : Hooge parameter in mono-Si αp : Hooge parameter in poly-Si Assumption: αm = αp=α carrier concentration p(x) metal contact mono-silicon Poly-silicon oxide base p(x) sox sm p(x) αp,Dp αm,Dm x1 x3 x2 0 Wm Wp L Diffusion fluctuation in SIB

  18. oxide permittivity barrier height for the minority carriers modified Planck’s constant area of IFO loss tangent of the oxide tunneling probability of minority carriers fluctuation in effective mass of minority carriers electronic charge Boltzmann constant IFO thickness Tunneling fluctuation in SIB

  19. Scaling effect on SIB AF for SIB in PNP transistors • Diffusion fluctuation dominant in large (0.7x100μm2) devices. • Tunneling fluctuation dominant in small (0.7x0.7μm2) devices.

  20. Scaling effect on SIB in PNP transistors with thickest IFO Total SIB Tunneling fluctuation component of SIB Diffusion fluctuation component of SIB

  21. ds Emitter plug effect in smaller device small device Large device • Thicker polysilicon in smaller transistors. • Lower dopant concentration; shallower junction. • higher chance for minority carriers from base to reach and tunnel through the oxide interface; tunneling fluctuation dominant. • FLUORINE EFFECT: fluorine enhances oxide break-up. • lower fluorine (from BF2) concentration causes less oxide breakup in smaller PNP devices; increased tunneling: (no fluorine in the transistors studied here) dl < ds Poly-Si emitter dl oxide mono-Si emitter base

  22. Perimeter depletion effect d1 < d2 • Polysilicon surface almost perpendicular to wafer surface at emitter window sidewall. • Reduced doping concentration in the perimeter region. • Shallower junction close to emitter window perimeter. • An overlap of the emitter-base space charge region with poly-mono silicon interface might occur close to perimeter. Poly-Si emitter d2 d1 oxide mono-Si emitter base

  23. Perimeter depletion effect in smaller transistors Perimeter/area vs. emitter area • For smaller transistors • perimeter/area ratio increases sharply. • non ideal peripheral component of base current increases. • fluctuation in non-ideal base current might become significant. Perimeter/area emitter area (μm2)

  24. Effect of IFO on DC characteristics of 0.7x100μm2 NPN transistors • IFO increases the current gain significantly.

  25. Effect of IFO on DC characteristics of 0.7x100μm2 PNP transistors • No significant improvement in current gain with increasing IFO thickness.

  26. Effect of interfacial oxide on SIB in NPN and PNP transistors 0.7x100 μm2 NPN 0.7x100 μm2 PNP • IFO increases SIB both in NPN and PNP transistors.

  27. Difference in the effect of IFO in NPN and PNP transistors 0.7x100μm2 transistors • In PNP, diffusion fluctuation in mono and poly-silicon emitter dominates; less effect of IFO. • In NPN, both diffusion fluctuation in mono and poly-silicon emitter, and tunneling fluctuation through IFO contribute.

  28. Physics behind difference in NPN and PNP transistors • Hole barrier height larger than electron barrier height at interfacial oxide: • minority carriers (holes) severely suppressed in NPN; significant current gain improvement. • minority carriers (electrons) not suppressed significantly in PNP; little current gain improvement. • Effect of fluorine: • fluorine accelerates oxide break-up. • fluorine from emitter dopant BF2 in PNP creates more oxide breakup; reduced tunneling and increased diffusion through broken oxide. • Increased oxide breakup and faster diffusion of boron makes the emitter deeper in PNP: • increased recombination-base current, reduced current gain improvement. • higher diffusion fluctuation in larger monosilicon emitter region. • Different oxidation rate of the base material could create different IFO thickness for NPN and PNP transistors on the same wafer.

  29. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  30. Effect of interfacial oxide on SIC 0.7x100 μm2 NPN 0.7x100 μm2PNP • IFO increases SIC both in NPN and PNP transistors.

  31. 1.E-05 0.7x100μm2 PNP, thickest IFO ) -1 (ohm carrier transport determined by electric field in base collector junction. Hooge type fluctuation at the collector side of base-collector junction. 22 1.E-06 (0.98) ~ I C output conductance h K=0.98 1.E-07 1.E-05 1.E-04 1.E-03 I (A) C Number fluctuation in SIC requires further investigation. SIC modeling Some researchers assign the same origin of SIB to SIC. is merely an amplified SIB.

  32. saturated drift velocity carrier concentration n(x) metal contact mono-silicon Poly-silicon oxide collector base WB 0 Diffusion fluctuation in SIC n(x) α,D

  33. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  34. Effect of bias on coherence in NPN and PNP transistors 0.7x100 μm2 PNP, thickest IFO, RS=1MΩ 0.7x100 μm2 NPN, thickest IFO, RS=1MΩ • Coherence decreases with increasing bias in NPN transistor.

  35. Effect of varying base bias resistance (RS) on SV 0.7x100 μm2 NPN, thickest IFO, IB=384nA • SVC does not decrease any more for RS smaller than 1 kΩ. • SVB becomes comparable to system background noise for RS smaller than 10 kΩ.

  36. SVC SVE 12V 4.8V RL RS 1K 100K RE Collector-emitter measurement setup

  37. Dominant noise source in collector-emitter measurement 0.7x100 μm2 NPN, thickest IFO, RS=100Ω Unity coherence. One single dominant noise source: SIC or SVr?

  38. SIC in collector-emitter measurement 0.7x100 μm2 NPN, RS=100Ω no physical explanation for such high current dependence: SPURIOUS?

  39. Effect of interfacial oxide on SVr 0.7x100 μm2 NPN, RS=100Ω

  40. Effect of internal resistance in collector-emitter measurement 0.7x100 μm2 NPN, thickest IFO Collector-base measurement, RS=1MΩ Collector-emitter measurement, RS=100Ω

  41. fluctuation in minority carrier tunneling oxide metal contact mono-silicon Poly-silicon base fluctuation in majority carrier tunneling tunneling probability of the majority carriers through IFO fluctuation in Tunneling fluctuation through interfacial oxide

  42. as high as 1.8V and as high 1 V found in literature. unique for each sample. Interfacial oxide thickness • Inconsistency: • uncertainty in loss tangent, mass and potential barrier of the carriers at oxide interface. • obtained from Kleinpenning et. al, IEEE Trans. on Elec. Dev., vol. 42, 1995.

  43. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  44. Simulation results vs. Measured Noise data measured at TI Experimental and Simulated data Simulated with modified model Experimental data Simulated with existing model

  45. Computer source code • Existing BERKELEY SPICE source code has been modified. • Source code written at Texas Instruments Inc. by Douglas Weiser. • and have been added to the existing noise model in addition to . • An area scaling factor has been added to the equations to make the noise models scalable. The modified BERKELEY SPICE source code is available to the SRC (Semiconductor Research Corporation) member companies (TI, Intel, IBM, Motorola, National Semiconductor Corporation, AMD, etc.)

  46. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  47. Device structure under investigation dielectric isolation SiGe epi-SiGe poly interface n+ poly Si emitter p+ SiGe epi p+ SiGe epi p+ SiGe poly p+ SiGe poly p SiGe epi shallow trench shallow trench Selectively implanted collector n+ Si emitter DTI (deep trench isolation) DTI (deep trench isolation) DTI (deep Trench isolation) z y x x = emitter-poly overlap y = composite enclosure of poly z = DTI enclosure of composite Transistors described as x-y-z; e.g. SIC:25-10-25.

  48. Dominant noise source • Calculated SVC/SVB with SIB contribution dominant closely matches experimental SVC/SVB ; SIB contribution dominant. • IB increases rπ decreases coherence increases.

  49. Outline • Introduction: • Limitations in existing noise models. • Importance and motivation of research. • Noise in polysilicon emitter bipolar transistors: • Experimental setup. • SIB modeling: • noise mechanisms, effect of bias, geometry and IFO. • SIC modeling: • noise mechanisms, effect of bias and IFO. • SVr modeling: • Collector-emitter measurement setup, effect of bias and IFO. • Computer codes. • Noise in SiGe heterojunction bipolar transistors: • Dominant noise source. • Effect of selective collector implant. • Effect of higher extrinsic base implant. • Effect of SiGe epi-SiGe poly interface. • Effect of emitter-poly overlap. • Physical origin and modeling of SIB. • Conclusion

  50. Selectively implanted collector (SIC) Higher collector-base capacitance Lower Higher collector doping Retarded Kirk-effect Higher Higher and reduced degradation of Reduced base-width by compensation of boron tail Selectively implanted collector

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