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MicroNet Digital Core Design

MicroNet Digital Core Design . ECE – 401 Senior Design Presentation. MicroNet Digital Core - Team. Team Members: CSU Student(s) Matt Heath – Digital Core Circuit (Hardware) Woodward Member(s) Clayton Rehbien – Project Sponsor Pat McKeon – Project Manager Tena Britt – Mentor

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MicroNet Digital Core Design

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  1. MicroNet Digital Core Design ECE – 401 Senior Design Presentation Created By: Matt Heath

  2. MicroNet Digital Core - Team • Team Members: • CSU Student(s) • Matt Heath – Digital Core Circuit (Hardware) • Woodward Member(s) • Clayton Rehbien – Project Sponsor • Pat McKeon – Project Manager • Tena Britt – Mentor • Rollins Linser – I/O Circuits (Hardware) • Dennis Belt – Lead Engineer • Dave Peterson – Software Engineer • Bill Becker - Marketing • Nancee Ault – Designer Created By: Matt Heath

  3. MicroNet Digital Core - Introduction Created By: Matt Heath

  4. MicroNet Digital Core – Overview • Reason for the Project • Current modules are facing parts obsolescence. • Intel 196 Family • Motorola DSP5600 Family • Discrete I/O • Circuit Design • Circuit and Layout re-use for all modules • Reduce circuit real estate on current modules Created By: Matt Heath

  5. MicroNet Digital Core – Current Goals • Goals / Deliverables: • Complete Detailed Requirements • Start Digital Core Circuit • Schematic • Board Layout Created By: Matt Heath

  6. MicroNet Digital Core – Application • Interface with the VME Bus • 32 bit data bus • 24 bit address bus • Other command signals • Interface with the I/O circuits • Discrete or Analog circuits • Health Monitoring • Other Specific Functions for Individual Modules Created By: Matt Heath

  7. MicroNet Digital Core – Design • Design is based on: • Marketing Requirements • Has to be backwards compatible • Has to support future architecture • Other issues with current module • Looked at past repair reports • Researched the Woodward knowledgebase articles Created By: Matt Heath

  8. MicroNet Digital Core – Design • Microprocessor Selection Created By: Matt Heath

  9. MicroNet Digital Core – Design • FPGA Design • Pin Count • I/O pins • Data and address pins • Signal pins (VME bus & module CPU interface) • Gate Amount • Received an approximate amount from Software Engineers Created By: Matt Heath

  10. MicroNet Digital Core – Design • Simulations – HyperLynx From Mentor Graphics Created By: Matt Heath

  11. MicroNet Digital Core – Design • Design Road blocks • Bus Voltage • FPGA – 3.3V • 565 – 2.6V • Sync. The FPGA with 565 Processor • Re-program the firmware when it is at the customer site. • Service Pack Style of distribution Created By: Matt Heath

  12. MicroNet Digital Core – Budget • Current Costs • Engineering Labor • $15,000 Note: Labor is for all people working on the project except me. • Material • Xilinx Spartan-3A FPGA Engineering Board • $230.00 • Future Costs • Circuit Board • $700.00/ circuit board • Engineering Labor • $200,000.00 Created By: Matt Heath

  13. MicroNet Digital Core – Future Goals for Spring Semester (ECE-402) • Goals/Deliverables • Digital Core Circuit Schematics • Digital Core Circuit Layout • Test Results for Circuit • Digital Core Specifications/Paperwork • Circuit Analysis  HyperLynx • Simulations  HyperLynx • Tolerance Stack-ups  MathCAD and Excel • Timing Margins HyperLynx Created By: Matt Heath

  14. MicroNet Digital Core – Conclusion Thank You! Created By: Matt Heath

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