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COMP290-052 FPGAs Internals Verilog Basics VGA Timing Assignment

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COMP290-052 FPGAs Internals Verilog Basics VGA Timing Assignment

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    1. COMP290-052 FPGAs Internals Verilog Basics VGA Timing Assignment Anselmo Lastra

    2. 2 What’s Inside FPGA? Basic logic building blocks Interconnect Configurable I/O pins Some high-end FPGAs have very complex components Multipliers (Spartan 3) Processors Fast I/O

    3. 3 Xilinx FPGA

    4. 4 Spartan2 4K bit RAM blocks Large amt of logic Program stored in SRAM

    5. 5 Switch Matrix

    6. 6 Pass Transistor

    7. 7 Logic Lookup Table Instead of gates So doesn’t matter much how you specify your logic Ends up truth table

    8. 8 Spartan 2 At right two logic cells (LC), a slice Two (four LCs) in CLB LUT is small RAM Can be used as RAM

    9. 9 CLB Muxes can make full 6-input function Can generate some functions w/ up to 19 inputs Each LC can be 1 bit of an adder

    10. 10 Xilinx IOB (abstract view)

    11. 11 Spartan 2 IOB

    12. 12 RAM One on XSA-100 card has 10 blocks for a total of 40Kbits SRAM

    13. 13 Clock de-skewing Clocks are delayed one cycle and synchronized across chip Can divide or multiply (2-4x) clock Can de-skew external clock signals (might be good for DRAM) See http://www.xilinx.com/xapp/xapp174.pdf

    14. 14 Spartan 2 Device Specs See http://direct.xilinx.com/bvdocs/publications/ds001_2.pdf

    15. 15 SpartanIIE and 3

    16. 16 Others Some devices with microprocessor and extra logic For control applications http://www.xilinx.com/products/tables/fpga.htm Can also synthesize controllers We have Xilinx software to generate processors Also opencores.org and other GNU-type sites

    17. 17 Verilog Chose it because It’s more C-Like than VHDL (Ada) The folks I know use it

    18. 18 Structural Verilog Explicit description of gates and connections Textual form of schematic Basically specify netlist You won’t write much this way

    19. 19 Structural Verilog module example_3_1_a(X,Y,Z,F); input X; input Y; input Z; output F; //wire X_n, Y_n, Z_n, f1, f2; not g0(X_n, X), g1(Y_n, Y), g2(Z_n, Z); nand g3(f1, X_n, Y_n), g4(f2, X_n, Z_n), g5(F, f1, f2); endmodule

    20. 20 Slight Variation – Gates not named module example_3_1_c(X,Y,Z,F); input X; input Y; input Z; output F; not(X_n, X); not(Y_n, Y); not(Z_n, Z); nand(f1, X_n, Y_n); nand(f2, X_n, Z_n); nand(F, f1, f2); endmodule

    21. 21 Assign The assign keyword used to make connections between nets RHS can specify combinational logic Example assign a = b;

    22. 22 Dataflow Description Basically a logical expression gates not explicit

    23. 23 Logical Operations Very similar to C or Java

    24. 24 Buses Denotes a set of wires input [1:0] S; Syntax is [a, b] where a is high-order So this could be “[0:1] S” Order matters when you make assignments and connect wires Don’t use syntax S [1:0]

    25. 25 4-to-1 Mux with Conditional module mux_4_to_1_dataflow(S, D, Y); input [1:0] S; input [3:0] D; output Y; assign Y = (S == 2'b00) ? D[0] : (S == 2'b01) ? D[1] : (S == 2'b10) ? D[2] : (S == 2'b11) ? D[3] : 1'bx; endmodule

    26. 26 Constants in Verilog Syntax [size][‘radix]constant Size in bits Radix can be d, b, h, or o (default d) Examples assign Y = 10; // Decimal 10 assign Y = ‘b10 // Binary 10, decimal 2 assign Y = ‘h10 // Hex 10, decimal 16 assign Y = 8‘b0100_0011 // Underline ignored Binary values can be 0, 1, or x

    27. 27 Hierarchical Design Hierarchy of modules Hierarchy automatically shown in ISE Example: 4-bit adder Design half adder Use in full adder Use full adder in 4-bit adder

    28. 28 Verilog Half Adder module half_adder_v(x, y, s, c); input x, y; output s, c; assign s = x ^ y; assign c = x & y; endmodule

    29. 29 Verilog Full Adder module full_adder_v(x, y, z, s, c); input x, y, z; output s, c; half_adder_v HA1(x, y, hs, hc), HA2(hs, z, s, tc); assign c = tc | hc; endmodule

    30. 30 4-Bit Adder (the hard way) module adder_4_v(B, A, C0, S, C4); input[3:0] B, A; input C0; output[3:0] S; output C4; wire[3:1] C; full_adder_v Bit0(B[0], A[0], C0, S[0], C[1]), Bit1(B[1], A[1], C[1], S[1], C[2]), Bit2(B[2], A[2], C[2], S[2], C[3]), Bit3(B[3], A[3], C[3], S[3], C4); endmodule

    31. 31 Behavioral Verilog // 4-bit Adder: Behavioral Verilog module adder_4_b_v(A, B, C0, S, C4); input[3:0] A, B; input C0; output[3:0] S; output C4; assign {C4, S} = A + B + C0; endmodule

    32. 32 How Far Can We Push This? Will synthesize multiplier Tried 16x16 – 140 Slices Won’t synthesize division Not a surprise Shifters ( << and >> ) OK

    33. 33

    34. 34 Register Data Type Usually causes latch or FF to be synthesized Examples reg state; reg [15:0] addr;

    35. 35 Always Block Example always @ (Set or Reset) statement; // often procedural Sensitivity list determines what might affect statements Can see beginnings as simulator Example next

    36. 36 Flip-Flop Example module dff_v(CLK, RESET, D, Q, Q_n); input CLK, RESET, D; output Q, Q_n; reg state; assign Q = state; assign Q_n = ~ state; always @(posedge CLK or posedge RESET) begin if (RESET) state <= 0; else state <= D; end endmodule

    37. 37 Blocking Assignment Equal sign indicates blocking statements initial begin B = A; C = B; end Result is that new contents of B are in C, so all have contents of A.

    38. 38 Non-Blocking Assignment <= indicates non-blocking statements initial begin B <= A; C <= B; end All RHS evaluated first, then assigned Or analogous hardware implementation Result is that old contents of B are in C

    39. 39 Not Software Don’t assign to same reg in more than one always block The always blocks are concurrent Probably doesn’t make sense to set reg from two signals Assignments in always blocks should be non-blocking Unless you mean sequential execution May synthesize differently

    40. 40 If Else One exists Note that always will try to synthesize FF; good example in book if (select) out <= A; If cover all possibilities, no FF if (select) out <= A; else out <= B;

    41. 41 Verilog Case Statement case (expression) case: statements; other case: statements; default: statements; // optional endcase Example in a moment

    42. 42 State Machine (Part I) module seq_rec_v(CLK, RESET, X, Z); input CLK, RESET, X; output Z; reg [1:0] state, next_state; parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;

    43. 43 Next State (II) always @(X or state) begin case (state) A: if (X == 1) next_state <= B; else next_state <= A; B: if(X) next_state <= C;else next_state <= A; C: if(X) next_state <= C;else next_state <= D; D: if(X) next_state <= B;else next_state <= A; endcase end

    44. 44 On Reset or CLK (III) always @(posedge CLK or posedge RESET) begin if (RESET == 1) state <= A; else state <= next_state; end

    45. 45 Output (IV) always @(X or state) begin case(state) A: Z <= 0; B: Z <= 0; C: Z <= 0; D: Z <= X ? 1 : 0; endcase end

    46. 46 Testing Generate simulation programs There’s a visual approach Test Bench Waveforms Limited Write Verilog Test fixture

    47. 47 Initial Statements run when program begins initial begin statements… end Useful/necessary for simulation

    48. 48 Initial not synthesized Warnings printed If you get tired, just bracket with //synopsys translate_off initial … end //synopsys translate_on

    49. 49 Timing/Delay You can indicate time scale at top of testbench file (units and time step) `timescale 1ns/1ns The # sign and an integer indicates a delay initial begin A = 4'd0; B = 4'd0; C0 = 1'b0; #50 A = 4'd3; B = 4'd4; end

    50. 50 Simple Testbench initial begin A = 4'd0; B = 4'd0; C0 = 1'b0; #50 A = 4'd3; B = 4'd4; #50 A = 4'd2; B = 4'd5; #50 A = 4'd9; B = 4'd9; #50 A = 4'd10; B = 4'd15; #50 A = 4'd10; B = 4'd5; C0 = 1'b1; #50 A = 4'd0; B = 4'd0; C0 = 1'b0; #50 A = 4'b1111; B = 4'b1111; C0 = 1'b1; end

    51. 51 Simple Loop Can use for statement in an initial block integer k; for(j = 0; j < 4; j = j + 1) begin #50 A = A + 1; end

    52. 52 Printing initial begin $monitor($time, "A=%b,B=%b, c_in=%b, c_out=%b, sum = %b\n", A,B,C0,C4,S); end The $monitor directive prints whenever any of the variables changes $display just prints; useful for headers See Verilog references

    53. 53 Demo Testbench Using ModelSim Can examine internal state of modules Drag net or register names to the left of the waveform window Then restart simulation

    54. 54 Things for You to Look Up parameter – way to make parameterized module General counter that can be resized, for example

    55. 55 VGA Signaling on XSA-100 RGB and two synchronization pulses, horizontal and vertical

    56. 56 VGA Timing You supply two pulses, hsync and vsync, that let the monitor lock onto timing One hsync per scan line One vsync per frame

    57. 57 Horizontal Timing Terms hsync pulse Back porch (left side of display) Active Video Video should be blanked (not sent) at other times Front porch (right side)

    58. 58 Horizontal Timing 640 Horizonal Dots Horiz. Sync Polarity NEG Scanline time (A) 31.77 us Sync pulse length (B) 3.77 us Back porch (C) 1.89 us Active video (D) 25.17 us Front porch (E) 0.94 us

    59. 59 Vertical Timing (note ms, not us) Vert. Sync Polarity NEG Vertical Frequency 60Hz Total frame time (O) 16.68 ms Sync length (P) 0.06 ms Back porch (Q) 1.02 ms Active video (R) 15.25 ms Front porch (S) 0.35 ms

    60. 60 Timing as Pixels Easiest to derive all timing from single-pixel timing How long is a pixel? Active video / number of pixels 25.17 us / 640 = 39.32ns Conveniently close to 25 MHz – just use that I calculated some, but also see http://www.epanorama.net/documents/pc/vga_timing.html

    61. 61 What To Do Make Verilog modules to generate hsync, vsync, horizontal count, vertical count, and signal to indicate active video Use that from higher-level to drive RGB using counts gated by active Can make test pattern, etc Later will add frame buffer DRAM

    62. 62 Stuff to Read Tutorials http://support.xilinx.com/support/techsup/tutorials/index.htm Manuals http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm Look at Xilinx Synthesis Technology (XST) manual. Has Verilog section. Verilog links on Alex Krstic’s page http://www.cs.unc.edu/~krstic/digital%20logic/verilog/

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