Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation

1. Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation Seokjin Lee*, D. F. Wong+ *Dept. of Electrical and Computer Engineering +Dept. of Computer Sciences The University of Texas at Austin

2. Outline • Overview • Introduction • FPGA Architecture, Routing resources • FPGA routing problem • Problem Formulation • Routing graphs and Timing graphs • Algorithm Description • Lagrangian Relaxation • LR_ROUTE, NET_ROUTE • Experimental Results • Conclusion

3. Overview • A new timing-driven routing algorithm for FPGAs • Find a routing with minimum critical path delay for a given placed circuit. • Handling of the timing constraints in a mathematical programming framework. • Routing results are compared with those of VPR router.

4. FPGA Architecture • Logic modules • Implements logic functions • LUTs, flip-flops • Routing resources • Wire segments • Programmable switches • I/O modules <A typical FPGA architecture>

5. FPGA Routing Resources • Prefabricated wire segments • Routing constraints : Sharing of a wire segments by different nets is not possible • Limited Routability • High RC delays and large area of switches

6. FPGA Routing

7. Routing Graph Gr (Vr , Er) • Vr : I/O pins of logic modules, wire segments • Er : feasible connections between the nodes • Routing problem: Find vertex disjoint trees T={T1,…Tn}

8. Timing Constraints • Source-to-sink delays of nets • Delay of wire-switch chains • Calculated from architecture specific RC values based on Elmore delay model • Timing constraints • Specified by arrival times at primary inputs (outputs of storage elements) or required times at primary outputs (inputs of storage elements)

9. Timing Graph Gt (Vt , Et) • Constructed from input netlist • Captures timing constraints • Vt : inputs, outputs, logic module pins • Et : source-sink pairs of nets, input-output pairs of logic modules • Fictitious nodes s : connects primary inputs, t : connects primary outputs

10. Timing-Driven FPGA Routing • Minimization of critical path delay under timing and routing constraints • Find vertex disjoint routing trees T = {T1, …, Tn} for all the nets such that Minimize subject to

11. Lagrangian Relaxation • General technique for solving optimization problems with difficult constraints • Lagrangian subproblems • New objective function: adding constraints to the original objective function after multiplied by constants (Lagrangian multipliers) • Iteratively update Lagrangian multipliers and solve Lagrangian subproblems

12. Lagrangian Relaxation Original problem Lagrangian subproblem

13. LR for Our Problem Original problem Lagrangian subproblem

14. Optimality Conditions • Optimality conditions on  • By rearranging terms,

15. Simplified Lagrangian Subproblem Optimality conditions on  Lagrangian subproblem becomes

16. Updating Lagrangian Multipliers Subgradient Method : stepsize

17. LR_ROUTE • Initialize  • Call NET_ROUTE to solve LS() • Computefor each • Update for each • Repeat Steps 2-4 until no shared resource exists.

18. Solving Lagrangian Subproblem • NET_ROUTE • Find routing trees T for a set of given multipliers such that Minimize subject to where

19. Solving Lagrangian Subproblem

20. Routing Nets • For net k, • Cost for each node:

21. NET_ROUTE • For each net k • Rip up routing for net k • for each sink v of net k • Maze route from source to sink with cost • Update for all nodes in

22. Experimental Results • FPGA model used • Symmetrical-array-based FPGA • Each logic block contains four 4-input LUTs and flip-flops • Switch connections: Fs = 3, Fc = W Fs: number of connectionsper wire entering the switch box Fc : number of tracks to which each logic block pin can connect W : number of tracks in a channel

23. Experimental Results • Tested on large circuits from MCNC benchmark • Routing with fixed channel width • Minimum channel width obtained by running VPR in timing-driven mode • Better results for 13 circuits (out of 17) • Critical path delay improved up to 33% with comparable runtime

24. Experimental Results • Critical path delay and runtime comparison

25. Experimental Results

26. Conclusion • A new timing-driven routing algorithm for FPGAs • Find a routing with minimum critical path delay for a given placed circuit. • Handling of the timing constraints by Lagrangian relaxation. • Routing results are better than those of VPR router.