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EMC Guidelines

EMC Guidelines. EMC guidelines. EMC should be taken into account at early design stage…. K. Armstrong, Advanced PCB design and layout for EMC. 2. EMC guidelines. Which problems? Know your enemy. Power integrity (PI). Signal integrity (SI). ESD, EFT, EOS. Conducted emission (CE).

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EMC Guidelines

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  1. EMC Guidelines

  2. EMC guidelines EMC should be taken into account at early design stage… K. Armstrong, Advanced PCB design and layout for EMC 2

  3. EMC guidelines Which problems? Know your enemy Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS Conducted emission (CE) Integrated circuits / electronic applications Radiated emission (RE) Radiated immunity (RI) Conducted immunity (CI) 3

  4. Summary • Golden Rules for low emission • Power supply routing strategy • Decoupling capacitance • Reduction of core noise • Reduction of IO noise • 2. Golden Rules for low susceptibility • Decoupling capacitance • Reduce rectification issues in analog circuits • Isolation of Noisy blocks • Improve noise immunity of IOs

  5. Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance • Inductance is a major source of resonance • Each conductor acts as an inductance • Ground plane modifies inductance value (worst case is far from ground) Reducing inductance decreases SSN !! Lead: L=0.6nH/mm Bonding: L=1nH/mm

  6. Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10nH Die of the IC bonding Long leads Far from ground PCB Flip chip package: L up to 3nH Short leads balls Die of the IC Close from ground Requirements for high speed microprocessors : L < 50 pH !

  7. Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use double/triple bonding on pins with large di/dt

  8. Golden Rules for Low Emission Correct Fail Rule 1: Power supply routing strategy B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs 9 I/O ports

  9. Golden Rules for Low Emission Current density simulation Layout view VDD / VSS VDD / VSS VDD / VSS Rule 1: Power supply routing strategy C) Place supply pairs close to noisy blocks Memory PLL Digital core

  10. Golden Rules for Low Emission EM field Current loop Added contributions Reduced contributions EM wave EM wave current current Die Lead Lead currents Rule 1: Power supply routing strategy D) Place VSS and VDD pins as close as possible • to increase decoupling capacitance that reduces fluctuations • to reduce current loops that provoke magnetic field

  11. Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: Case 1 : Infineon Tricore Case 2 : virtex II Worst case not enough supply pairs, bad distribution & dissymmetry Not ideal Not enough supply for IOs : (core emission is lower than IO one)

  12. Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: 2 FPGA , same power supply, same IO drive, same characteristics Supply strategy very different ! • More Supply pairs for IOs • Better distribution courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com

  13. Golden Rules for Low Emission Rule 1: Power supply routing strategy Case 1: low emission due to a large number of supply pairs well distributed Case 2: higher emission level (5 times higher) courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com

  14. Golden Rules for Low Emission Rule 2: Add decoupling capacitance Bulk capacitor (Low frequency) HF capacitor (ceramic) PCB – Power / ground plane Package and IC Power source Voltage converter / regulator Ferrite Vdd Vss 1 µF – 10 mF Ground reference 100 nF – 1 nF 1 nF Transistors, gates, interconnects

  15. Golden Rules for Low Emission Rule 2: Add decoupling capacitance • Equivalent model of a PDN (the most basic model…) PDN Circuit activity Vdd Power supply voltage bounce: ZPDN ΔVdd IIC gnd • Ensuring power integrity relies on the control of a low impedance of the PDN. • A target impedance ZT can be defined as a design objective: ZPDN Zt Frequency Target frequency range 15

  16. Golden Rules for Low Emission Local charge tank In time domain In frequency domain Large capacitors reduce PDN impedance. Large capacitors react rapidly to charge demand. Rule 2: Add decoupling capacitance Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand) Voltage bounce v(t) • Principle: Voltage regulator IC Vdd Vss Vdd PCB Vss Decoupling capacitor i(t) 16

  17. Golden Rules for Low Emission 10 – 15 dB Efficient on one decade 10-100 nF decoupling Rule 2: Add decoupling capacitance • Effect of on-board capacitors: No decoupling X7R 50 V ceramic capacitors Customer’s specification Parasitic emission (dBµV) 80 70 60 50 40 100 µF electrolytic capacitor 30 20 10 0 -10 1 10 100 1000 Frequency (MHz) 17

  18. Golden Rules for Low Emission Rule 2: Add decoupling capacitance • Example: decoupling of a 16 bit microcontroller (dspic33F). • The circuit produces a significant amount of noise over the range 1 – 500 MHz. • We select Zt = 2 Ω. IC Current (1 Ω probe) Z PDN (VNA measurement) Board + IC without decap Antiresonance ZT With 6×100 nF decap 18

  19. Golden Rules for Low Emission Rule 2: Add decoupling capacitance • Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. • Measurement of power supply voltage in time domain (16 I/O pads switch simultaneously). 19

  20. Golden Rules for Low Emission Rule 2: Add decoupling capacitance On chip decoupling capacitance versus technology and complexity: Intrinsic on-chip supply capacitance 65nm 100nF 90nm 0.18µm 10nF 0.35µm 1.0nF 100pF Devices on chip 10pF 100K 1M 10M 100M 1G

  21. Golden Rules for Low Emission Rule 2: Add decoupling capacitance • Effect of on chip capacitance: smooth on-chip voltage fluctuation and reduce conducted emission. • Example: two versions of a CMOS 90 nm digital core, Vdd = 1.2 V, same mounting board: • Core 1: No on-chip decoupling capacitance • Core 2 : Add 100 pF MIM decoupling capacitance 1 ohm conducted measurement Vdd bounces measurement 59 mV 27 mV A. Boyer (LAAS-CNRS) 21

  22. Golden Rules for Low Emission Rule 2: Add decoupling capacitance • Add limited serial resistor to smooth the voltage drops (too much resistor would increase IR drop and slow down the decap response !) • Effectiveness of decap cells depends on proximity to power supply noise sources. J. Rabaey, Low Power Design Essentials, 2008

  23. Golden Rules for Low Emission Rule 3: Reduce core noise • Reduce operating supply voltage • Reduce operating frequency • Reduce peak current by optimizing IC activity, using distributed clock buffers, turning off unused circuitry, avoiding large loads, creating several operation mode

  24. Golden Rules for Low Emission Rule 3: Reduce core noise • Optimization of bus clock: reduction of buffer’s drive, spread the switching in order to reduce the current peak. J-P. Leca “Microcontrollers Electromagnetic Interferences Modeling and Reduction”, PhD report, Univ of Nice, France, 2012

  25. Golden Rules for Low Emission Clock out Clock in T+/-Δt T Pseudorandom noise Spread spectrum frequency modulation P f +/-Δf specification +/-Δf f 1/T Rule 3: Reduce core noise • Add a controlled jitter on clock signal to spread the noise spectrum

  26. Golden Rules for Low Emission Rule 3: Reduce core noise - Spread Spectrum Frequency Modulation • Reduction or spreading of clockharmonics by frequency modulation. • Example : sinus clockatFc = 100 MHz vs modulated sinus clock: Carrier frequency Fc = 100 MHz Modulation frequency FM= 1 MHz Frequency excursion dF = +/- 5 MHz  Modulation index md = 5 Reduction of narrow band RF energy Spread spectrum over B Carson rule: 26

  27. Golden Rules for Low Emission Rule 3: Reduce core noise - Spread Spectrum Frequency Modulation • Add a controlled jitter on clock signal to spread the noise spectrum • In practice, a triangular signal is used as modulating signal. Freq. modulation ΔF Clock out Clock in Tc Tc+/-dt Frequency Modulated clock +/- dt Modulant t Carson rule applies also: TMod dP Modulated clock If Fmod < RBW (reso BW of the receiver): B Unmodulated clock 27

  28. Golden Rules for Low Emission Rule 3: Reduce clock noise – Spread Spectrum Frequency Modulation • Real case study: Effect on emission spectrum produced by the PLL of a 32 microcontroller • Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/- 0.64 MHz. • Receiver bandwidth = 10 KHz. Average reduction of 64 MHz harmonics = 10.6 dB A. Boyer (LAAS-CNRS) 28

  29. Golden Rules for Low Emission Rule 4: Reduce I/O noise • Reduction of the fast rate of I/O current. • Minimize the number of simultaneous switching lines (bus coding) • Reduce di/dt of I/O by controlling slew rate and drive Tr1 Tr2 SR & Drive control Emission level f 1/Tr2 1/Tr1

  30. Golden Rules for Low Emission Rule 4: Reduce I/O noise • Example: I/O buffer with Drive and slew rate control options: Full or reduced drive, high and limited slew rate. • Impact of I/O options on timing waveform: Rise time = 2 ns Rise time = 8.6 ns Full Drive – High slew rate Reduced Drive – High slew rate 30

  31. Golden Rules for Low Emission Rule 4: Reduce I/O noise • Impact of I/O options on timing waveform and output drive current: What is the more « emissive » option ? The less emissive ? 31

  32. Golden Rules for Low Emission Rule 4: Reduce I/O noise • Comparison of conducted emission (1 ohm method) 32

  33. Golden Rules for Low Emission Rule 4: Reduce I/O noise • Comparison of conducted emission (1 ohm method) 33

  34. Origin of electromagnetic emission Rule 5: Reduce SSN • The switching of output buffer contributes to a large part of conducted and radiated emission. When several I/O switches simultaneously, their contributions tend to add: Simultaneous Switching Noise. • Minimize the number of simultaneous switching lines (bus coding) Effect of the number of simultaneous switching buffers 16 output buffers, two different switching sequences. 34

  35. Golden Rules for Low susceptibility Rule 1: Decoupling capacitance is also good for immunity Immunity level (dBm) • DPI aggression of a digital core • Reuse of low emission design rules for susceptibility • Efficiency of on-chip decoupling combined with resistive supply path Decoupling capacitance Substrate isolation No rules to reduce susceptibility Work done at Eseo France (Ali ALAELDINE) Frequency

  36. Golden Rules for Low susceptibility Rule 1: Decoupling capacitance is also good for immunity • Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. • Measurement of conducted immunity (harmonic signal coupled on power supply plane according to DPI standard). At each harmonic frequency, the disturbance power is increased until a circuit failure arises. Max. Power 36

  37. Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits • The following circuits are concerned by the EMI-induced DC offset: opa, voltage regulator, bandgap reference, current mirror, analog output • EMI rectification on a simple analog circuit: Non linear behaviour Once the EMI reaches the non-linear node, the DC offset cannot be filtered DC offset

  38. Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits • Example: harmonic injection (100 MHz) on the power supply of a bandgap reference voltage

  39. Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits • EMI injection in operational amplifier inputs (weak distortion): Differential current offset: RF disturbances Current source Parasiticcapacitors Non linear relation ID2 ID1 • Offset depends on: • Voltage coupled on diff input and common source X • OpAmp bandwidth • Parasitic capacitor CN and Cs • Non linear behavior of MOS devices Diff. Pair in saturation regime

  40. Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits • Non linearity and parasitic capacitances are the origin of EMI-induced offset in analog circuits (op-amp, output analog buffer, current mirror, voltage reference ..) • Immunity improvement strategies: • Filter the noise before it reaches a sensitive node (RC filter or increase of input capacitance in differential pair) • Reduce parasitic capacitor • Increase circuit bandwidth • Linearization of input devices • EMI-induced offset cancellation (e.g. cross-coupled differential pair)

  41. Golden Rules for Low susceptibility Rule 3: Isolate Noisy blocks • Example of substrate coupling issue: disturbance of a bandgap voltage reference by the switching of a DC-DC converter embedded within the same circuit Disturbance of bandgap due to substrate coupling A. Boyer (LAAS-CNRS) DC-DC converter output switching

  42. Golden Rules for Low susceptibility Bulk isolation Noisy blocks Standardcells Far fromnoisy blocks Analog Separate supply Images perturbation DCDC  bandgap Rule 3: Isolate Noisy blocks • Why ? • To reduce the propagation of switching noise inside the chip • To reduce the disturbance of sensitive blocks by noisy blocks (auto-susceptibility) • How ? • by separate voltage supply • by substrate isolation • by increasing separation between sensitive blocks • By reducing crosstalk and parasitic coupling at package level

  43. Golden Rules for Low susceptibility Rule 4: Improve noise immunity of IOs • Add Schmitt trigger on digital input buffer • Use differential structures for analog and digital IO to reject common mode noise • Rectification issues due to ESD protection activation during conducted injection (especially with dV/dt triggering structures) 2 dB Schmitt trigger

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