1 / 53

Design guidelines for EMC of electronic devices

Design guidelines for EMC of electronic devices. Summary. Introduction Guidelines for signal integrity Guidelines for power integrity Guidelines for reduced radiated emission Reduction of I/O noise Spread-spectrum frequency modulation. January 20. Introduction.

nkimberly
Télécharger la présentation

Design guidelines for EMC of electronic devices

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Design guidelines for EMC of electronic devices

  2. Summary Introduction Guidelines for signal integrity Guidelines for power integrity Guidelines for reduced radiated emission Reduction of I/O noise Spread-spectrum frequency modulation January 20

  3. Introduction EMC should be taken into account at early design stage… K. Armstrong, Advanced PCB design and layout for EMC January 20

  4. Introduction Why taking into account EMC for ICs ? K. Armstrong, Advanced PCB design and layout for EMC 4

  5. Introduction Which problems? Know your enemy Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS Conducted emission (CE) Integrated circuits / electronic applications Radiated emission (RE) Radiated immunity (RI) Conducted immunity (CI) January 20

  6. Design guidelines for EMC Guidelines for signal integrity January 20

  7. Guidelines for signal integrity Signal integrity (SI) issue Zc ; Tp VL VG Criterion for SI issue: Overshoot VL or VG if Tr is the rising or falling time of a signal, SI issues due to the propagation of the EM wave along the transmission line arise if: Vdd VIH Undetermined level Undershoot VIL Ringing 0 t Longer setting time January 20

  8. Guidelines for signal integrity Signal integrity (SI) issue K. Armstrong, Advanced PCB design and layout for EMC January 20

  9. Guidelines for signal integrity Ensuring Signal integrity – Rule 1 Cancel reflection coefficient at each line terminals by impedance matching Impedance matching of a uniform transmission line with constant characteristic impedance Zc. • Practical designs for a digital transmission: Vcc Zc Zc Rs Rpd Rpd Ct Rs : serial resistor= Rdriver - Zc Rpd : pull down resistor = Zc January 20

  10. Guidelines for signal integrity Ensuring Signal integrity – Rule 2 Control the characteristic impedance of transmission line (PCB track, package) and avoid line discontinuities • Microstrip line configuration: W εr I t h Ideal ground plane January 20

  11. Guidelines for signal integrity Ensuring Signal integrity – Rule 2 • Example: consider the following PCB stack-up. A digital link between 100 Ω driver and receiver is ensured by a microstrip line routed in layer 4. • Propose a value for the line width. January 20

  12. Guidelines for signal integrity Ensuring Signal integrity – Rule 3 Ensure a controlled and short return current path. • Place a full ground plane in microstrip line. • Avoid slot in return plane (e.g. ground plane) • Keep a symmetry (avoid unbalance in the return current path) • Avoid routing of critical signals along board edge. CORRECT BAD January 20

  13. Guidelines for signal integrity Ensuring Signal integrity – Rule 4 If available, use on-chip techniques to improve signal integrity • On-chip termination, programmable output driver impedance • Pre-emphasis/De-emphasis, equalization (Xilinx) 5Gbps - Without pre-emphasis 5Gbps - With pre-emphasis (Altera)

  14. Guidelines for signal integrity Crosstalk • Example: voltage measurement at 3 terminals of two 20 cm long parallel PCB tracks. • The first line is excited by a pulse generator, the second is terminated by two resistive loads. Origin of effects on both lines ?

  15. Guidelines for signal integrity Crosstalk Trace 1 (emitter) Trace 2 (victim) d W W I1’ I1 Crosstalk = near-field coupling εr I2 V h Parasitic return current path “Normal” return current path Evaluate the crosstalk in the case study. 15 January 20

  16. Guidelines for signal integrity Ensuring Signal integrity – Rule 5 Increase the isolation between emitter and victim lines • Increase the distance between traces (rule 3 W = “the separation between traces must be 3 times the width of the trace as measured from centerline to centerline of two adjacent traces”) < 3W W W t (εr = 4.5) h Substrate ground 16 January 20

  17. Design guidelines for EMC Guidelines for power integrity January 20

  18. Guidelines for power integrity Power Distribution Network Ensuring a stable power/ground voltage reference (ΔVdd < 5% Vdd nominal) Bulk capacitor (Low frequency) HF capacitor (ceramic) PCB – Power / ground plane Package and IC Power source Voltage converter / regulator Ferrite Vdd Vss 1 µF – 10 mF Ground reference 100 nF – 1 nF 1 nF Transistors, gates, interconnects 18 January 20

  19. Guidelines for power integrity Power integrity (PI) issue Power supply source (regulator, DC-DC converter) PDN ΔVdd Noisy Integrated circuit Vdd PDN i(t) ΔVss Vss IR noise Circuit Power supply bounce 19 January 20 Delta-I noise

  20. Guidelines for power integrity Power integrity (PI) issue • Example: Measurement of the power supply voltage fluctuation of a digital circuit Low frequency contribution High frequency contribution Switching Switching Switching Noise with a large frequency content and some major resonance modes 20 January 20

  21. Guidelines for power integrity Ensuring power integrity – Rule 1 Maintain PDN impedance below the target impedance • Equivalent model of a PDN (the most basic model…) PDN Circuit Vdd Power supply voltage bounce: ZPDN ΔVdd IIC gnd • Ensuring power integrity relies on the control of a low impedance of the PDN. • A target impedance ZT can be defined as a design objective: ZPDN Zt Frequency Target frequency range 21 January 20

  22. Guidelines for power integrity Ensuring power integrity – Rule 2 Reduce interconnect parasitic (mainly inductance) of power and ground connections • Use traces as wide as possible for Vdd and Vss connections • i.e. use power and ground planes • Be careful of the common impedance of Vdd and Vss connections (finite impedance, even for ground plane): Single point grounding with serial circuits Direct grounding to a reference ground plane 22 January 20

  23. Guidelines for power integrity Ensuring power integrity – Rule 2 2.1) Use shortest interconnection to reduce the serial inductance • Inductance is a major source of resonance • Each conductor acts as an inductance • Ground plane modifies inductance value (worst case is far from ground) Reducing inductance decreases SSN !! Lead: L=0.6nH/mm Bonding: L=1nH/mm January 20

  24. Guidelines for power integrity Ensuring power integrity – Rule 2 2.1) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10nH Die of the IC bonding Long leads Far from ground PCB Flip chip package: L up to 3nH Short leads balls Die of the IC Close from ground Requirements for high speed microprocessors : L < 50 pH ! January 20

  25. Guidelines for power integrity Ensuring power integrity – Rule 2 2.2) Use enough Vdd/Vss pairs Case 2 : Texas Instruments OMAP3630 (Application processor) Case 1 : Micron T46H64M16LF Mobile LP DDR SDRAM 515 I/O pins, 110 power supply pins, 80 ground pins 60 I/O pins, 8 power supply pins, 7 ground pins January 20

  26. Guidelines for power integrity Local charge tank In time domain In frequency domain Large capacitors reduce PDN impedance. Large capacitors react rapidly to charge demand. Ensuring Power integrity – Rule 3 Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand) Voltage bounce v(t) • Principle: Voltage regulator IC Vdd Vss Vdd PCB Vss Decoupling capacitor i(t) 26 January 20

  27. Guidelines for power integrity Ensuring Power integrity – How choosing decoupling capacitor ? • If ideal capacitor, only one decoupling capacitor per power domain would be enough: • Cdec: the minimum capacitor able to provide a current to the circuit without any large voltage fluctuations. • ΔVddmax : max allowed voltage fluctuation • ΔI : current peak absorbed by the circuit • tr : rise time of the current peak 27 January 20

  28. Guidelines for power integrity Ensuring Power integrity – How choosing decoupling capacitor ? • Case study 2 : decoupling of FPGA power supplies. • Two power domains: Core domain (1.2 V) and I/O domain (3.3 V) • Transient current estimation: • Core domain: Ipeak = 2 A during 10 ns • I/O domain: 196 I/Os, typ. rise/fall time = 2 ns, typ. load = 20 pF • Propose a budget of decoupling capacitors 28 January 20

  29. Guidelines for power integrity Ensuring Power integrity – How choosing decoupling capacitor ? • Case study 2 : decoupling of FPGA power supplies. • Recommendations from the manufacturer: • Plus all the recommendations about PDN routing and capacitor placement ! 29 January 20

  30. Guidelines for power integrity Ensuring Power integrity – Real decoupling capacitors • Impedance profile in frequency domain: X7R 50 V ceramic capacitors On which frequency range are these decoupling capacitors really efficient ? 100 µF electrolytic capacitor 30 January 20

  31. Guidelines for power integrity Ensuring Power integrity – How choosing decoupling capacitor • Methodology to optimize the choice of decoupling capacitors: Define Zt Board model Regulator model Circuit(s) model PDN without decoupling model Define freq. range of decoupling Fmin Fmax Compute ZPDN YES If ZPDN(f) > Zt for f in [Fmin;Fmax] NO Add capacitor(s) and/or change capa values Capacitors model Power integrity OK – Decoupling budget January 20

  32. Guidelines for power integrity Ensuring Power integrity – How choosing decoupling capacitor • Example: decoupling of a 16 bit microcontroller (dspic33F). • The circuit produces a significant amount of noise over the range 1 – 500 MHz. • We select Zt = 2 Ω. IC Current (1 Ω probe) Z PDN (VNA measurement) Board + IC without decap ZT With 6×100 nF decap 32 January 20

  33. Design guidelines for EMC Guidelines for reduced radiated emission January 20

  34. Guidelines for reduced radiated emission Radiated emission – basic mechanisms • Radiated emissions come from interconnects excited by a transient current or voltage. They become parasitic antennas. • Two basic radiated mechanisms: • Dipole antenna (electric) • high impedance load (I/O loaded by high impedance) • E field proportional to length l • Loop antenna (magnetic) • Low impedance load (power supply, I/O loaded by low impedance • H field proportional to surface S Electric field Magnetic field Circuit Circuit I Clock VSS VDD Length l High Z load Surface S 38 January 20

  35. Guidelines for reduced radiated emission Reducing radiated emission – Rule 1 Reduce parasitic antenna (length or surface) to reduce differntial and common mode radiation • Identify current loops on PCB and reduce their surface. • Place decoupling capacitors as close as possible to IC pins. • Use power or ground plane to reduce current loop surface. • Reduce the length of interconnects which carry high frequency signals. Circuit Circuit VDD VDD Decoupling capacitor VSS VSS Decoupling capacitor Id Id Smaller loop  Reduced radiated differential mode Large loop  High radiated differential mode 39 January 20

  36. Guidelines for reduced radiated emission Reducing radiated emission – Rule 2 Control the current return path to reduce common mode Example 2: one differential output buffer with a non symmetrical routing Example 1: one Vdd pin but two Vss pins IVdd = IVSS1+IVSS2 Power Differential buffer I+ ≠ I- Circuit IVdd I+ VDD D+ VSS2 VSS1 I- D- IVss1 Parasitic coupling GND IVSS2 Ic 40 January 20

  37. Guidelines for reduced radiated emission Reducing radiated emission – Rule 3 Use a “good” ground plane(s) to shield noisy interconnects • Use coplanar or stripline configuration to shield noisy interconnect. • A “good” reference plane is equipotential at any point ! • Connect two reference plane witth same potential by vias regular interval less than λ/20 ! Correct connection between two planes with same potential Stripline configuration Ref plane line GND via Ref plane GND 41 January 20

  38. Guidelines for reduced radiated emission Radiated emission – Case study – Student project • Basic digital applications routed on a 2 layer board with the auto-router function of the board design tool. Only one 100 nF decoupling capacitor for all the application. • Measurement of radiated emission in TEM cell. Limit CISPR25

  39. Guidelines for reduced radiated emission Radiated emission – Case study – Student project • Numerous EMC design rules violation: large power-ground loops, long fast clock interconnect, return path not ensured by a ground plane… • Change the placement & routing of the board by starting to place Vdd/Vss and fast clock, add a ground plane on both side. • Design rule violation examples: Large loop Vdd connection CMOS inverter Vss connection Equivalent surface of fast clock interconnect “High speed” clock source 43

  40. Guidelines for reduced radiated emission Radiated emission – Case study – Student project Top layer Effect of placement & Routing improvement (still one 100 nF decoupling capacitor) -30 dB Bottom layer 44 January 20

  41. Design guidelines for EMC Reduction of I/O noise January 20

  42. Reduction of I/O noise Rule1: As I/Os are one of the most contributor to radiated or conducted emission, reduce I/O noise • Reduction of the fast rate of I/O current. • Minimize the number of simultaneous switching lines (bus coding) • Reduce di/dt of I/O by controlling slew rate and drive Tr1 Tr2 SR & Drive control Emission level f 1/Tr2 1/Tr1 January 20

  43. Reduction of I/O noise Reduce I/O noise – Case study • Example: I/O buffer with Drive and slew rate control options: Full or reduced drive, high and limited slew rate. • Impact of I/O options on timing waveform: Rise time = 2 ns Rise time = 8.6 ns Full Drive – High slew rate Reduced Drive – High slew rate January 20

  44. Reduction of I/O noise Reduce I/O noise – Case study • Impact of I/O options on timing waveform and output drive current: What is the more « emissive » option ? The less emissive ? January 20

  45. Reduction of I/O noise Reduce I/O noise – Case study • Comparison of conducted emission (1 ohm method)

  46. Reduction of I/O noise Reduce I/O noise – Case study • Comparison of conducted emission (1 ohm method) January 20

  47. Design guidelines for EMC Spread-spectrum frequency modulation January 20

  48. Spread spectrum frequency modulation Frequency modulation • Frequency modulation spreads the spectrum of a signal • Example : sinus clock at Fc = 100 MHz vs modulated sinus clock: Carrier frequency Fc = 100 MHz Modulation frequency FM= 1 MHz Frequency excursion dF = +/- 5 MHz  Modulation index md = 5 Reduction of narrow band RF energy Spread spectrum over B Carson rule: 52 January 20

  49. Spread spectrum frequency modulation Clock in Rule1: Reduce noise from clock or PWM signals by using Spread Spectrum Frequency Modulation (SSFM) • Principle: Unmodulated clock (carrier) Freq. modulation ΔF Clock out Tc Tc+/-dt Frequency Modulated clock +/- dt Modulant t Carson rule applies also (for fundamental frequency): TMod dP Modulated clock What is the amplitude reduction? B Unmodulated clock 53

  50. Spread spectrum frequency modulation Emission improvement • The reduction of spectrum amplitude depends on: • Parameters of the modulation (md and Fm) • The modulant waveform (selection of a waveform that makes the spectrum as flat as possible) • Receiver bandwidth RBW: P RBW dP Measured SSFM signal P unmodulated EMI receiver f SSFM B P Measured SSFM signal f RBW B f 54 B

More Related