AID-EMC Automotive IC Design for Low EMC

1. AID-EMCAutomotive IC Design for Low EMC Review Meeting 29 augustus 2006 VILVOORDE

2. Agenda • Structure of the IWT project • Progress per workpackage • WP1: • WP2: • WP3: • WP4: • Status Deliverables • Resources used • Cooperation • Conclusions

3. Structure of the project

4. WP1: Specifications and measurements

5. WP1: Technical problems • Nearly impossible to achieve

6. T1.1: Correlation between different test set-ups • Target is to increase current handling

7. T1.2: Influence of PCB and attached cabling • VDMOS is more stable and robust

8. T1.3: Validation of the ICEM model • Need for additional • Selection

9. T1.4: Characterization of the coupling paths • Need for additional • Selection

10. T1.5: Measurements • Need for additional • Selection

11. Contributions by partners • AMIS • Aa • bb • KUL-ESAT • aa • KHBO • cc

12. WP1: Innovation Realised • Improved

13. WP2: EMC susceptibility of analogue circuits

14. WP2: Technical problems • LDMOS • Surface

15. T2.1: Finalization of the LIN driver • Design • Use

16. T2.2: Design DC current regulator with low EMS • ESD

17. T2.3: Design input structure with low EMS • Optimize

18. T2.4: Design input structure with high common mode rejection • Optimize

19. T2.3: Design guidelines for low EMS • Optimize

20. Contributions by partners • AMIS • Aa • bb • KUL-ESAT • aa • KHBO • cc

21. WP2: Innovation Realised • New • Better • Guidelines • Technical Risks • Protection • Protection

22. WP3: Digital techniques

23. WP3: Technical problems • Logic families with reduced current variation • how logic circuits can be designed in such a way that they generate less current variation (di/dt) in the supply lines • EMC-friendly clock strategy • how the electromagnetic radiation caused by digital circuits can be reduced by adapting the clock strategy.

24. T3.1: Design of EMC-friendly logic families - I • Selection of EMC-friendly logic family: • 6 different logic design techniquesare compared, • The design goal is to reduce di/dt noise while still keep the compromise on the speed, power, area trade-off under control, • Based on the simulations, we conclude that CSL logic is the best choice. • Comparison of CSL and SCMOS: • The CSL logic produces an amount of di/dt noise almost 36dB smaller than the SCMOS logic, • If controlled properly, we can keep the power of CSL circuit comparable to the SCMOS, • CSL show a smaller area per logic function for complex digital gates and systems.

25. T3.1: Design of EMC-friendly logic families - II But there is static power !! Current Steering Logic (Static + Dynamic) Area di/dt Peak-Peak Power Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Ring Oscillator of 21-stages

26. T3.1: Design of EMC-friendly logic families - III Power spectrum density of di/dt comparison 36dB SCMOS CSL

27. T3.2: EMC-friendly clock strategies - I 2 different clock strategies are studied: • Clock skew:based on the introduction of different skews to the branches of a clock tree. • Only 2-5dB reduction, • Need smart algorithm to control and optimize the skew. • Spread Spectrum Clock Generation(SSCG): based on an existing DLL idea. • Spread the clock period by a programmable amount, • Fully digital and simple implementation, • More than 12dB on the maximum di/dt power spectrum reduction.

28. T3.2: EMC-friendly clock strategies - II Regular Clock Spread Spectrum Clock 12dB reduction Zoom in • A test chip for SSCG will be designed to prove the simulation(next project phase). • Problem remains: introduction into a standard design flow. Spectrum from 300MHz to 800MHz

29. T3.3: Test chip for the EMI Suppressing Regulator - I • The EMI suppressing regulator replaces the EMC-friendly logic: • Control the way the current delivered to the internal digital core, hence keep the EMI under control, • Compatible with conventional CMOS logic, • Large EMI reduction is ensured (40dB), comparable with low noise digital cells only, • More power efficient than low noise logic cells, • Can be adjusted to a wide range of chip size and power consumption level.

30. T3.3: Test chip for the EMI Suppressing Regulator - II 9x106 7x103 ~60 dB reduction 40dB (EMI regulator) + 20dB (Serial regulator) load current of digital core current of Vbat di/dt of Vbat di/dt of V3v3 FFT FFT di/dt p-p =8.5x104 [A/s] di/dt p-p =1.8x109 [A/s]

31. T3.3: Test chip for the EMI Suppressing Regulator - III EMI Suppressing regulator Micrograph of the RD2E test chip and the EMI suppressing regulator

32. T3.3: Test chip for the EMI Suppressing Regulator - IV Measurements di/dt@Vbat > 5x reduction di/dt@source TBD: • figure out low current capability problem, • detailed measurements will be ready in 2nd phase

33. Contributions by partners • AMIS • Deliver specifications for the chip, • Deliver design kit, • Process the chip, • Evaluate the chip measurement results. • KUL-ESAT-MICAS • Scientific analysis, • Chip design, • Chip measurements. • KHBO • Advice on the EMC measurements.

34. WP3: Innovation Realized • Innovative characters: • It addresses the problem of electromagnetic radiation at its very source, • A systematic approach for radiation reduction is developed (includes a EMI suppressing regulator). • A clever clock design strategy to guarantee low EMI is designed.

35. WP4: Computer-aided EMC analysis

36. WP4: Technical problems • Technical problem

37. T4.1: Models for EMS simulation framework • Improve

38. T4.2: Development of EMS simulation framework • Design

39. T4.3: Automated generation of EM-inclusive behavioral models • The best

40. T4.4: Industrial EMC design flow • The best

41. Contributions by partners • AMIS • Aa • bb • KUL-ESAT • aa • KHBO • cc

42. WP4: Innovation Realised • Self-protecting • Know-how • Design guidelines • Technical risks • Conflicting • aaa

43. Status Deliverables • Main result:

44. Cooperation • Flemish partners • KUL ESAT • KHBO • AMIS

45. Resources (1)

46. Resources (2)

47. Conclusions • 38% basis funding percentage

48. ? Silicon Solutions for the Real World!