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The CPU in more detail…

The CPU in more detail…. Programs and data are stored in memory Memory usually refers to RAM, but we use the more general term memory to also include the caches The CPU executes program instructions and processes data The CPU performs the following: Fetches instructions and data from memory

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The CPU in more detail…

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  1. The CPU in more detail… • Programs and data are stored in memory • Memory usually refers to RAM, but we use the more general term memory to also include the caches • The CPU executes program instructions and processes data • The CPU performs the following: • Fetches instructions and data from memory • Decodes and executes instructions • Stores results back into memory (to be displayed on the screen or stored onto disk or…) • Goes to the next instruction (if there is one)

  2. CPU: High-Level Layout CPU Instructions and data go from Mem to CPU Memory(or memory hierarchy) Registers Data Bus ControlUnit Processed data (results) go from CPU to Mem ALU Memory contains data and instructions CPU contains a control unit, the ALU, and registers

  3. CPU: a closer look… Instruction cycle: execution of a single program instruction by the CPU • Fetch: control unit loads instruction from memory location in PC into IR • Decode: control unit interprets instruction • Execute: control unit executes instruction (tells ALU what to do) • PC is incremented to next program instruction and cycle repeats Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: PC: Program Counter R1: General Purpose Register 1 04: Data Bus 00 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR M6 R1 07: 200 AC: Accumulator 08: …

  4. Example Instruction Set Instruction set: basic set of operations the CPU can perform

  5. Example Program Execution Let’s start with a simple program that will add two values in memory and store the result in another location in memory. Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 00 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 07: 200 AC: Accumulator 08: …

  6. Example Program Execution Program begins by the operating system… • Loading the instructions and data into memory • Setting the program counter to the starting instruction (ex: PC=0) • The CPU is always performing the Fetch-Decode-Execute cycle, so the program then begins immediately Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 00 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 07: 200 AC: Accumulator 08: …

  7. Example Program Execution First pass of Fetch-Decode-Execute instruction cycle: • Fetch: instruction at memory location in PC (00) is loaded into IR Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 00 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 06 R1 07: 200 AC: Accumulator 08: …

  8. Example Program Execution First pass of Fetch-Decode-Execute instruction cycle: • Fetch: instruction at memory location in PC (00) is loaded into IR • Decode: control unit decodes the message Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 00 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 06 R1 07: 200 Move memory value to register AC: Accumulator 08: …

  9. Example Program Execution First pass of Fetch-Decode-Execute instruction cycle: • Fetch: instruction at memory location in PC (00) is loaded into IR • Decode: control unit decodes the message • Execute: control unit moves value in memory to a register Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 00 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 06 R1 07: 200 Move memory value to register AC: Accumulator 08: …

  10. Example Program Execution First pass of Fetch-Decode-Execute instruction cycle: • Fetch: instruction at memory location in PC (00) is loaded into IR • Decode: control unit decodes the message • Execute: control unit moves value in memory to a register • Increment program counter (PC) to next instruction (PC=01) Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 01 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 06 R1 07: 200 AC: Accumulator 08: …

  11. Example Program Execution 2nd instruction cycle: • Fetch: instruction at memory location in PC (01) is loaded into IR Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 01 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 07 R2 07: 200 AC: Accumulator 08: …

  12. Example Program Execution 2nd instruction cycle: • Fetch: instruction at memory location in PC (01) is loaded into IR • Decode: control unit decodes the message Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 01 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 07 R2 07: 200 Move memory value to register AC: Accumulator 08: …

  13. Example Program Execution 2nd instruction cycle: • Fetch: instruction at memory location in PC (01) is loaded into IR • Decode: control unit decodes the message • Execute: control unit moves value in memory to a register Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 01 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 07 R2 200 07: 200 Move memory value to register AC: Accumulator 08: …

  14. Example Program Execution 2nd instruction cycle: • Fetch: instruction at memory location in PC (01) is loaded into IR • Decode: control unit decodes the message • Execute: control unit moves value in memory to a register • Increment program counter (PC) to next instruction (PC=02) Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 02 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MMR 07 R2 200 07: 200 AC: Accumulator 08: …

  15. Example Program Execution 3rd instruction cycle: • Fetch Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 02 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 ADD R1 R2 200 07: 200 AC: Accumulator 08: …

  16. Example Program Execution 3rd instruction cycle: • Fetch • Decode Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 02 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 ADD R1 R2 200 07: 200 Add values in registers, store in accumulator AC: Accumulator 08: …

  17. Example Program Execution 3rd instruction cycle: • Fetch • Decode • Execute Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 02 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 ADD R1 R2 200 07: 200 Add values in registers, store in accumulator AC: Accumulator 08: 300 …

  18. Example Program Execution 3rd instruction cycle: • Fetch • Decode • Execute • Increment PC Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 03 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 ADD R1 R2 200 07: 200 AC: Accumulator 08: 300 …

  19. Example Program Execution 4th instruction cycle: • Fetch Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 03 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MAM 08 200 07: 200 AC: Accumulator 08: 300 …

  20. Example Program Execution 4th instruction cycle: • Fetch • Decode Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 03 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MAM 08 200 07: 200 Move value in accumulator to memory AC: Accumulator 08: 300 …

  21. Example Program Execution 4th instruction cycle: • Fetch • Decode • Execute Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 03 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MAM 08 200 07: 200 Move value in accumulator to memory AC: Accumulator 08: 300 300 …

  22. Example Program Execution 4th instruction cycle: • Fetch • Decode • Execute • Increment PC Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 04 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 MAM 08 200 07: 200 AC: Accumulator 08: 300 300 …

  23. Example Program Execution 5th instruction cycle: • Fetch Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 04 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 HLT 200 07: 200 AC: Accumulator 08: 300 300 …

  24. Example Program Execution 5th instruction cycle: • Fetch • Decode Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 04 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 HLT 200 07: 200 End of the program! AC: Accumulator 08: 300 300 …

  25. Example Program Execution 5th instruction cycle: • Fetch • Decode • Execute: ask OS for new PC value (next program to run) Memory CPU 00: MMR 06 R1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: MMR 07 R2 02: ADD R1 R2 03: MAM 08 PC: Program Counter R1: General Purpose Register 1 04: HLT Data Bus 04 100 05: IR: Instruction Register R2: General Purpose Register 2 06: 100 HLT 200 07: 200 End of the program! AC: Accumulator 08: 300 300 …

  26. More Complex Example: Loop • Let’s compute power of 2! • Let’s sketch the algorithm needed: • Use two variables X and Y(X will store our powers and Y will store the multiplier 2) • Initialize: X=1, Y=2 • Repeat the following operations: X = X*Y • Will this work? Yes! • Begin: X=1, Y=2 • Loop1: X=X*Y X=2, Y=2 • Loop2: X=X*Y X=4, Y=2 • Loop2: X=X*Y X=8, Y=2 • … how do we make it stop? Worry about that later…

  27. More Complex Example: Loop Let’s write the assembly program: 00: Storage for starting X (1) 01: Storage for multiplier Y (2) 02: Storage for Result (powers of 2) 03: INP 1 00 // PUT VALUE 1 IN MEM[00] 04: INP 2 01 // PUT VALUE 2 IN MEM[01] 05: MMR 00 R1 // COPY MEM[00] (“1”) TO REG1 06: MMR 01 R2 // COPY MEM[01] (“2”) TO REG2 07: MUL R1 R2 // ACCUMULATOR = REG1*REG2 08: MAR R1 // COPY ACCUMULATOR TO REG1 09: MAM 02 // COPY ACCUMULATOR TO MEM[02] 10: JMP 07 // LOOP: JUMP TO MEM[07] MEM DATA PROGRAM

  28. More Complex Example: Loop • OS loads program into memory • OS sets program counter, PC=03 • Program execution begins! Memory CPU 00: Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 03 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 07: MUL R1 R2 AC: Accumulator 08: MAR R1 09: MAM 02 10: JMP 07 …

  29. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 04 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 INP 1 00 07: MUL R1 R2 Put value 1 into MEM[00] AC: Accumulator 08: MAR R1 09: MAM 02 10: JMP 07 …

  30. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 05 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 INP 2 01 07: MUL R1 R2 Put value 2 into MEM[01] AC: Accumulator 08: MAR R1 09: MAM 02 10: JMP 07 …

  31. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 06 1 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MMR 00 R1 07: MUL R1 R2 Copy MEM[00] to R1 AC: Accumulator 08: MAR R1 09: MAM 02 10: JMP 07 …

  32. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 07 1 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MMR 01 R2 2 07: MUL R1 R2 Copy MEM[01] to R2 AC: Accumulator 08: MAR R1 09: MAM 02 10: JMP 07 …

  33. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 08 1 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MUL R1 R2 2 07: MUL R1 R2 AC = R1*R2 AC: Accumulator 08: MAR R1 2 09: MAM 02 10: JMP 07 …

  34. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 09 2 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MAR R1 2 07: MUL R1 R2 Copy AC to R1 AC: Accumulator 08: MAR R1 2 09: MAM 02 10: JMP 07 …

  35. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 2 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 10 2 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MAM 02 2 07: MUL R1 R2 Copy AC to MEM[02] AC: Accumulator 08: MAR R1 2 09: MAM 02 10: JMP 07 …

  36. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 2 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 07 2 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 JMP 07 2 07: MUL R1 R2 Jump to MEM[07]PC=07 AC: Accumulator 08: MAR R1 2 09: MAM 02 10: JMP 07 …

  37. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 2 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 08 2 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MUL R1 R2 2 07: MUL R1 R2 AC = R1*R2 AC: Accumulator 08: MAR R1 4 09: MAM 02 10: JMP 07 …

  38. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 2 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 09 4 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MAR R1 2 07: MUL R1 R2 Copy AC to R1 AC: Accumulator 08: MAR R1 4 09: MAM 02 10: JMP 07 …

  39. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 4 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 10 4 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MAM 02 2 07: MUL R1 R2 Copy AC to MEM[02] AC: Accumulator 08: MAR R1 4 09: MAM 02 10: JMP 07 …

  40. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 4 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 07 4 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 JMP 07 2 07: MUL R1 R2 Jump to MEM[07]PC=07 AC: Accumulator 08: MAR R1 4 09: MAM 02 10: JMP 07 …

  41. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 2 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 08 4 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MUL R1 R2 2 07: MUL R1 R2 AC = R1*R2 AC: Accumulator 08: MAR R1 8 09: MAM 02 10: JMP 07 …

  42. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 2 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 09 8 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MAR R1 2 07: MUL R1 R2 Copy AC to R1 AC: Accumulator 08: MAR R1 8 09: MAM 02 10: JMP 07 …

  43. More Complex Example: Loop Fetch-Decode-Execute instruction cycle • Fetch • Decode • Execute • Increment PC Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 8 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 10 8 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 MAM 02 2 07: MUL R1 R2 Copy AC to MEM[02] AC: Accumulator 08: MAR R1 8 09: MAM 02 10: JMP 07 …

  44. More Complex Example: Loop Infinite loop! • Program writes powers of 2 to MEM[02] forever! • Let’s make it terminate when we reach 8 Memory CPU 00: 1 Control Unit Fetches Decodes Executes instructions ALU Performs arithmetic and logic ops as instructed by CU 01: 2 02: 8 03: INP 1 00 PC: Program Counter R1: General Purpose Register 1 04: INP 2 01 Data Bus 07 8 05: MMR 00 R1 IR: Instruction Register R2: General Purpose Register 2 06: MMR 01 R2 JMP 07 2 07: MUL R1 R2 Jump to MEM[07]PC=07 AC: Accumulator 08: MAR R1 8 09: MAM 02 10: JMP 07 …

  45. More Complex Example: Loop MEM 00: Storage for starting X and termination value (8) 01: Storage for multiplier Y (2) 02: Storage for Result (powers of 2) 03: INP 1 00 // PUT VALUE 1 IN MEM[00] 04: INP 2 01 // PUT VALUE 2 IN MEM[01] 05: MMR 00 R1 // COPY MEM[00] (“1”) TO REG1 06: MMR 01 R2 // COPY MEM[01] (“2”) TO REG2 07: INP 8 00 // RE-USE MEM[00], PUT VAL 8 08: MUL R1 R2 // ACCUMULATOR = REG1*REG2 09: MAR R1 // COPY ACCUMULATOR TO REG1 10: MAM 02 // COPY ACCUMULATOR TO MEM[02] 11: MMR 00 R2 // COPY MEM[00] (“8”) TO REG2 12: SUB R2 R1 // ACCUMULATOR = REG2 – REG1 13: JPZ 16 // IF AC=0 (REG=REG2) GOTO MEM[16] 14: MMR 01 R2 // COPY MEM[01] (“2”) BACK INTO REG2 15: JMP 08 // LOOP: JUMP TO MEM[08] 16: HLT // END OF THE PROGRAM DATA PROGRAM

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