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MAVEN Digital/FPGA Peer Review STATIC FPGA May 12, 2010

MAVEN Digital/FPGA Peer Review STATIC FPGA May 12, 2010. D. Gordon. STATIC FPGA. Suprathermal & Thermal Ion Composition STATIC FPGA is the RTAX2000S-1CG624E Advanced testing phase: AX2000-1CG624 (same footprint – fused device)

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MAVEN Digital/FPGA Peer Review STATIC FPGA May 12, 2010

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  1. MAVEN Digital/FPGA Peer Review STATIC FPGA May 12, 2010 D. Gordon

  2. STATIC FPGA Suprathermal & Thermal Ion Composition STATIC FPGA is the RTAX2000S-1CG624E Advanced testing phase: AX2000-1CG624 (same footprint – fused device) Initial Development phase: A3PE3000-FG324 (FLASH device) via the “FPGA Daughter Board” 10K R-Cells, 21K C-Cells, 36Kbytes Internal SRAM Initial protoboard uses the A3PE3000-PQ208 In use for over 6 months, partial implementation System Clock = 24MHz – independent onboard oscillator Estimated Power: 560mW (160mW I/O; 400mW Core) typical 950mW (170mW I/O; 780mW Core) at 70C Utilization Estimate ~40% modules; 140 I/Os (constrained by FPGA daughter card to ~200 max) Block RAM: 1 block for RAWEV memory and 8 blocks for EVACCUM (out of 64 block total)

  3. STATIC BLOCK DIAGRAM

  4. STATIC Common Subsystems Design Features shared with other Instrument FPGAs Command & Telemetry Interfaces (CDI functionality for receiving commands and sending messages) Housekeeping Control and Message Format Memory Control Fixed and Sweep DAC Control Timing Backbone STATIC cycle is 4 seconds – divided into 1024 accumulation intervals Lookup table memory and control (Loader and Checksummer) High Voltage turn-on protected command Overcurrent Protection (shown in SWEA block diagram) to be implemented identically in STATIC

  5. STATIC Event Processing Four Pulses (TIMEA, TIMEB, TIMEC, TIMED) indicate frontend activity The EVPC module can be configured for flexible event acceptance criteria via the EVCONVLUT Special option to accept/reject “STOPFIRST” events ADC Readout is TDC1 (TIMEA-TIMEC) (TOF), TDC2 (TIMEB-TIMED) (TOF), TDC3 (TIMEA-TIMEB) (POS), TDC4 (TIMEC-TIMED) (POS)

  6. STATIC Binning and Products Configurable Anode and Mass Binning builds 1024-element 16-bit accumulator (EACC) every cycle (double-buffered) Accumulator uses FPGA internal memory Products are generated once/cycle using the EACC Memory P1 sums over all A and D (64M x 64E) P2 sums over all A and M (16D x 64E) P3 sums over all M (16A x 4Dx16E) P4 is configurable: RAM: Sum over all A (8D x 32E x 32M) CONIC: (16A x 4D x 16E x 16M) PICKUP (16A x 4D x 32E x 8M) APP_SCAN: Sum over all D (16A x 32E x 8M)

  7. STATIC Telemetry Options Fast Rates FAST Rate Messages can be generated along with event messages, or in FAST RATE only mode FAST RATE Only mode counts events, but no conversions Raw Event Mode Generate List of Converted Events Configurable number of events per message (1 to 32) Event buffer maintained in FPGA internal memory Telemetered every Accumulation Interval (3.8ms) Products Buffered and transmitted in the following cycle Any or all of the four Product types can be enabled

  8. STATIC Test Pulser Two Test Pulses (Start and Stop) Configurable frequency (~100Hz to ~2MHz) Configurable delay between pulses Variable Frequency Mode Sweeps during 4s cycle from 240Hz to 1MHz Variable Delay Mode

  9. STATIC Design Status Implemented/Exercised Command Interface Message (Telemetry) Subsystem Timekeeping DAC Subsystems Raw Event Processing Test Pulser Memory Control Pending Anode and Mass Binning Product Generation LUT Checksummer Event Decimation ECC or TMR for Internal FPGA Memory

  10. Backup Slides

  11. TDC Pulse Processing B A Start Anode Preamp A Preamp B C D Start Input A Stop Anode Start Input B Preamp C Preamp D Stop Input D Stop Input C Constant Fraction Disc B Constant Fraction Disc A Constant Fraction Disc C Constant Fraction Disc D TDC SECTOR C/D TDC TOF A/C TIMEC TIMED TDC TOF B/D /TIMEC /TIMED /TIMED TIMEA /TIMEC TIMEB TDC SECTOR A/B TIMEA TIMEB /TIMEA /TIMEB Title Block Diagram Size Document Number Rev B <Doc> A Date: Friday, April 06, 2007 Sheet 1 of 1

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