0xf1d0 Interim Review

1. 0xf1d0Interim Review Rod Green (rdg@ece.cmu.edu) Eric Haas (haas@ece.cmu.edu) Ming Luo (mluo@ece.cmu.edu) James Shuma (shuma@ece.cmu.edu)

2. Architectural Features and Design Goals • Architectural Features • Modularity • Design Goals • Make it work. • Modularity • Parallelism • Make it run fast.

3. Performance Against Schedule For more detail see http://www.ece.cmu.edu/~shuma/0xf1d0/sched.html

4. rdg’s Most ImportantTechnical Lessons Learned • General knowledge of MP3 algorithm • General knowledge of hc11 architecture • All knowledge learned from splitting mp3 code up and trying to make it easier to port

5. rdg’s Codesign Lessons Learned

6. rdg’s Wish List • Down with managers! Down with managers :)

7. haas’s Most ImportantTechnical Lessons Learned • I am a slacker. So far, I haven't actually designed any of the components that are going to be used in our final design. However, I have worked a lot on communication and I've designed a few prototypes to testconcepts put forth. There were some interesting timing issues that I hadn't thought about that came up when we were working on designing our protocols. But really, the only thing I've learned about technically is SuperLog. I've been reading up on SuperLog these past few weeks, and I like the things that SuperLog adds to Verilog. Unfortunatly, synplify doesn't work for .slg files, though, so I'm going to have to switch back to verilog for my next two milestones that are going to go on the FPGA. I've also been reminded about my tendancy to rewrite components at least a couple of times before I'm satisified with them.

8. haas’s Codesign Lessons Learned • There doesn't seem to be as much work on the hardware side for our design as there is for software. Most of the projects I've looked in this class and elsewhere at seem to be similarly unbalanced one way or the other, though, so this doesn't appear to be abnormal.

9. haas’s CAD Tools Lessons Learned • Since I'm the ``hardware guy,'' I have barely touched Hiware, so I can't really comment on it's usefulness or lact thereof. I haven't really exploited SuperLog anywhere near the extent of its capabilities, but it seems to be really nice from my perspective to do things from both software and hardware design perspectives and still be able to put the two together. Interfaces are a big win, as are the multiple types of fork and join. This is one tool that I hope I'll get more of a chance to use in the future, both in this class and afterwards. Max+Plus II is a strange tool, it isn't quite intuitive, but it could be far worse. The worst thing I've run into is that you have to import things and compile and place them in a certain order, or things won't work the way you think that they should and become a real pain to fix.

10. haas’s Wish List • The only group member that I've really had a problem with is myself. We haven't had perfect communication, but we really haven't had the major problems that I've had with classes I've taken or projects I've worked on in the past, but we haven't been perfect either.

11. mluo’s Most ImportantTechnical Lessons Learned • A fully wired up component does not equal a working component. • How to communicate with the processors and how they will communicate with each other and the fpga. • Make sure to see if the fpga works with the ram in, but not when it’s NOT in!

12. mluo’s Codesign Lessons Learned

13. mluo’s Codesign Lessons Learned • When designing a huge system, try to modularize things as much as possible. • In order to facilitate the design of complicated components, it is best to make sure it works in simulation first, and then move on to actual implementation.

14. mluo’s CAD Tools Lessons Learned • HIWare works, but only when all your settings are right. • MaxPlus+II is a pain to set up if you are not careful.

15. mluo’s Wish List • The successful completion of our project well within our rigorous completion schedule.

16. shuma’s Most ImportantTechnical Lessons Learned • Processors are really complex • Even when you think you’re writing synthesizable Verilog and Synplify doesn’t complain, you might end up with nothing but wires running straight from input to output. Check the synthesized logic.

17. shuma’s Codesign Lessons Learned • To make a complex system: • Build a framework • Build high-level descriptions of modules • Iteratively implement those high-level modules

18. shuma’s CAD Tools Lessons Learned • Hiware is not a CAD tool. • Superlog will be really useful someday.

19. shuma’s Wish List • Perfect communication • When people need help, they say so. • When people think others aren’t performing, they say so. • When people are being lazy, they say so.

20. jsmolens+545’s Most Important Technical Lessons • When in doubt, give it dirty looks.

21. jsmolens+545’s Codesign Lessons Learned • I believe that there should be a universal code sign, so that people know when code is nearby.

22. jsmolens+545’s CAD Tools Lessons Learned • SystemC is the best CAD tool there has been and will ever be. • Code should always be self-commenting

23. jsmolens+545’s Wish List • I wish I had more groups like 0xf1d0.