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Horizontally Partitioned Hybrid Memory Using Phase Change Memory (PCM) Technology

This paper explores the innovative concept of horizontally partitioned hybrid memory, integrating Phase Change Memory (PCM) into computing systems. PCM is a non-volatile memory technology that offers smaller cell sizes than DRAM, resulting in cost-effective solutions and the potential to replace traditional DRAM. The study addresses key challenges such as optimal allocation and migration policies, along with hardware support for memory access monitoring. It also discusses simulation frameworks and implementation strategies for improving memory management in modern processors, ensuring efficiency and performance.

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Horizontally Partitioned Hybrid Memory Using Phase Change Memory (PCM) Technology

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  1. Horizontally Partitioned Hybrid Main Memory with PCM Santiago Bock Daniel Mossé

  2. Phase Change Memory (PCM) • Emerging memory technology • Non-volatile (material changes) • Smaller cells than DRAM (less costly) • Cheap/fast reads, expensive/slow writes (melts material) • Possible DRAM replacement

  3. Horizontal Hybrid Memory • Hybrid Memory: • Small DRAM with large PCM • Horizontal(no “cached” data) • Single address space partitioned into DRAM and PCM • Operating system manages contents • Challenges: • What is the best allocation policy? • What is the best migration policy? • How can hardware monitors collect information about memory accesses? • How can hardware support migration?

  4. The Simulator Trace Reader Trace Reader Allocation Policy Memory Manager CPU CPU Migration Policy Cache Cache Shared Cache Simulation Engine Hybrid Memory DRAM PCM

  5. Basic Knowledge needed • Computer Architecture • Modern processorsand caches • TLB • DRAM • Operating Systems • Virtual memory • Memory management • Programming • C++ • Scripting

  6. Sample Projects • Suggesting NEW, BETTER Migration Policies • Implementation of a “Perfect” migration policy • Implementation of other policies • Improvements to the Simulator • Implementation of an out of order CPU • Implementation of a memory bus • Large Scale Study • More benchmarks • More parameters • More policies

  7. PCM Emulation Project • Emulate slow PCM • Memory accesses to far nodes are slower • Thread on far node emulates slow writes • Challenges • Limited information about the architecture • Latency is difficult to control CPU CPU CPU CPU Node 0 Node 1 DRAM 0 DRAM 1

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