“LAYOUT” EFFECTS HOW LAYOUTS CAN CHANGE CMOS AND HOW DO CIRCUIT SIMULATIONS ACCOUNT FOR THE CHANGE

“LAYOUT” EFFECTSHOW LAYOUTS CAN CHANGE CMOSAND HOW DO CIRCUIT SIMULATIONS ACCOUNT FOR THE CHANGE BOB PEDDENPOHL MODELING MANAGER CYPRESS MODELING CENTER LEXINGTON, KY 04/04/07

AGENDA (ACRONYM TEST) BSIM BASICS, NEW FEATURES BERKLEY SHORT CHANNEL IGFET MODEL STI EFFECT OR LOD EFFECT SHALLOW TRENCH ISOLATION OR LENGTH OF DIFFUSION WPE WELL PROXIMITY EFFECTS OPC OPTICAL PROXIMITY CORRECTION

AGENDA BSIM BASICS, NEW FEATURES LENGTH-OF-DIFFUSION (LOD) WELL PROXIMITY EFFECTS (WPE) OPTICAL PROXIMITY CORRECTION (OPC)

BSIM BASICS SPICE SIMULATION OF MOS (ONLY APPROXIMATIONS!) HAND CALC: Ids = width/length * Cox * Mobility * (Vgs – Vth - Vdsat) * Vds SPICE CALC: Ids = w/l * 1/TOX * U0 * (Vgs – VTH0 – VDSAT) * Vds TERMINOLOGY SPICE MODEL PARAMETERS (BSIM3 PARAMETERS) INSTANCE PARAMETERS SIMULATION PARAMETERS (BIAS CONDITIONS) MODEL EXAMPLE: .model nshort.1 nmos TOX = 4.19e-9 NETLIST EXAMPLE: m1 d g s b nshort w =25 l=0.5 m=1 ad=50 pd=27..delvth0=0.0 sa=1.04 sb=1.04 v1 g s 1.8 v2 d s 0.9 v3 b s 0.0 COMMAND RUN EXAMPLE spectre mynetlist.scs WAVEFORM VIEWER TO REVIEW SPECTRE OUTPUT FILES

BSIM3 VS BSIM4 WHAT ARE UPGRADES IN BSIM4? LOD WPE RF MODELING IMPROVEMENTS BSIM: http://www-device.eecs.berkeley.edu/~bsim3/ BSIM = BERKELEY SHORT-CHANNEL IGFET MODEL

MODEL DEVELOPMENT PROCESS SELECT “GOLDEN” WAFER MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

Sa Sb Sa Sb Sa Sb LAYOUT CHOICES & LOD • BEST VALUE FOR Sa, Sb? WHY BIGGER DIFFUSIONS?

Sa Sb Sa Sb MEASURED DATA • VTH DUE TO STI STRESS Sa, Sb Instance params for LOD STI Effect Proximity Effect

LOD MODEL EQUATIONS Sa Sb STRESS MODEL PARAMETERS f(Sa,Sb)

Sa Sb Sa Sb SPICE WITH LOD EFFECTS • BEST VALUE FOR Sa, Sb? WHY? • NETLIST WITH LOD m1 d g s b nshort w =25 l=0.5 m=1 ad=50 pd=27..delvth0=0.0 sa=1.04 sb=1.04 • IDS SPICE APPROX WITH LOD SPICE CALC: Ids = w/l * 1/TOX * (U0 + KU0) * (Vgs – VTH0 – VDSAT) * Vds • ALTERNATIVES TO MODELING? • MODEL  INSTANCE PARAMETERS + MODEL PARAMETERS • DRC  ENFORCE SINGLE SA, SB VALUE ALLOWED • CORNER MODELS  PUT WIDER VARIATION INTO MODEL • ADVANTAGES/DISADVANTAGES? • SIMULATION TIME & ACCURACY, MODEL DEVELOPMENT TIME • SILICON AREA INCREASES

WPE BACKGROUND • WHAT’S THE CAUSE? • http://www.ieee-cicc.org/06-8-6.pdf nwell Wspc Wspc

RECALL PROCESSING STEPS

NWELL IMPLANT EFFECTS CMOS • HIGH ENERGY ATOMS BOUNCE OFF PHOTORESIST • http://www.ieee-cicc.org/06-8-6.pdf (see paper diagrams) • WHY WPE NOW? • HIGH ENERGY IMPLANTERS • WANT DEEP IMPLANT  LOW RES PATH  SUPRESS BJT LATCHUP • SPICE MODEL OF WPE • Vth = VTH0 + KVTHOWE*(sca+WEB*scb + WEC*scc) • Vth@Vbs = K2 + K2WE * (sca + WEB*scb +WEC*scc) • Mobility = U0 * (1+KU0WE*(sca + WEB*scb+WEC*scc) • REFERENCE: • COMPACT MODEL COUNCIL WEBSITE • BSIM4 MANUAL FROM BERKELEY WEBSITE

SPICE WITH WPE EFFECTS nwell • INSTANCE PARAMS ALL FUNCTION Wspc • Sca, scb, scc • NETLIST WITH WPE m1 d g s b nshort w =25 l=0.5 m=1 ad=50 pd=27..delvth0=0.0 sca=1.1 scb=0.5, scc=3 • IDS SPICE APPROX WITH WPE SPICE: Ids = w/l * 1/TOX * (U0 + f(KU0WE) * (Vgs – VTHO + f(KVTHOWE) – Vdsat) * Vds • ADVANTAGES/DISADVANTAGES/ALTERNATIVES? Wspc

Is performance the same? RF FET Modules Layout With poly proximity bars M=2 M=4 Standard Layout Without poly proximity bars

OPC BACKGROUND OPTICAL PROXIMITY CORRECTION (OPC) DURING LIGHT EXPOSING OF PHOTORESIST FINAL SHAPES ON SILICON NOT MATCH DRAWN SHAPES BASED ON SURROUNDING ENVIRONMENT With proximity bars Standard Layout Without proximity bars

Sa Sb Sa Sb MEASURED DATA • VTH DUE TO STI STRESS Sa, Sb Instance params for LOD STI Effect Proximity Effect

MEASURED DATA • VTH DUE TO PROXIMITY AND STI STRESS STI Effect Proximity Effect

DRAWN NOT EQUAL FINAL OPC “SIMULATION” TOOL  IN: LAYOUT, OUT: POLY SHAPES Lcenter Ledge Ltrans

M=2 AND M=4 COMPARISON • SAME DRAWN L, BUT SILICON VARIES

DESIGNING WITH OPC • NO SPICE MODEL EFFECT • RELY ON CLDRC, NOT PERFECT • L(DRAWN) = L(SI) • ACCOUNT FOR IN YOUR DESIGN?

Sa Sb Sa Sb MEASURED DATA • VTH DUE TO PROXIMITY AND STI STRESS STI Effect Proximity Effect

CONCLUSIONS • LOD/WPE IMPACT TRANSISTOR PERFORMANCE, ACCOUNT FOR BY: • MODEL  ACCURATE AT COST OF MODEL DEVELOPMENT • DRC RULES  EASIER DESIGN KIT AT COST OF AREA • NEW PHYSICAL EFFECTS RELY HEAVILY ON INSTANCE PARAMETERS OR CLDRC • INTERACTION OF THE MODEL WITH CAD TOOLS • GOOD DESIGNER: • LIMIT THESE EFFECTS AS MUCH AS POSSIBLE IN LAYOUT • REVIEW MODELS TO ENSURE EFFECTS ARE INCLUDED

APPENDIX

EXECUTIVE SUMMARY • PROBLEM STATEMENT • TRANSISTOR PARAMETRIC SHIFTS DUE TO PROXIMITY EFFECTS • PHOTO/ETCH: DENSE VS ISOLATED • STI STRESS: POLY-STI EDGE SPACING • WHAT WAS DONE • ELECT/OPTICAL CHAR OF DENSE VS ISOLATED ON L8 • PHOTO/ETCH VS STI STRESS CHAR ON S8 • WHAT NEEDS TO BE DONE (TO BE FORMALIZED)

MEASUREMENTS: COMPLETE MOS • FET DC (VTH0, RDSW) • FET AC (CGDO,DLC) • DIODE DC (JS,JSW) • DIODE AC (CJ, CJSW)

Stress Equations in Model • Measurements done by SBJ • As NMOS gets closer to STI Edge, VT Increases, IDS and Gm Decrease • As PMOS gets closer to STI Edge, |VT| Decreases, IDS and Gm Increase. • STI induced Stress degrades NMOS and enhances PMOS characteristics (why enhanced?) • More measurements are planned. • Data is plotted for # of proximity bars and length of diffusion (LOD).

L = 0.158-0.008=0.15um at center L=0.222-0.008 = 0.214um at edge Transition region from edge before L becomes 0.15um  0.17um Impact will be larger for W=1.65 W=3.01 L=0.15 M2

L = 0.158-0.008=0.15um at center L=0.232-0.008 = 0.234um at edge of center two fingers L=0.212-0.008 = 0.204um at edge of outer fingers Transition region from edge before L becomes 0.15-0.155um = 0.185um W=3.01 L=0.15 M4

“LAYOUT” EFFECTS HOW LAYOUTS CAN CHANGE CMOS AND HOW DO CIRCUIT SIMULATIONS ACCOUNT FOR THE CHANGE