1 / 20

HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER CIRCUIT FOR RADIO FREQUENCY SIGNAL

HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER CIRCUIT FOR RADIO FREQUENCY SIGNAL. Kyusun Choi. Computer Science and Engineering Department. The Pennsylvania State University. Goal. Core Development and Silicon Test of 6-bit and 8-bit TIQ Based Flash ADC. High speed circuit and layout design

inga
Télécharger la présentation

HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER CIRCUIT FOR RADIO FREQUENCY SIGNAL

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER CIRCUIT FOR RADIO FREQUENCY SIGNAL Kyusun Choi Computer Science and Engineering Department The Pennsylvania State University

  2. Goal Core Development and Silicon Test of 6-bit and 8-bit TIQ Based Flash ADC • High speed circuit and layout design • Prototype chip fabrication • Test and evaluate, explore and improve

  3. Plan • Design 6 bit and 8 bit TIQ based ADC circuits and CMOS layouts • Fabrication of prototype chip in 0.25 m CMOS logic technology • Test prototype chip, extract parameters • Redesign 6 bit and 8 bit TIQ based ADC circuits and CMOS layouts • Fabrication of prototype chip in 0.25 m or 0.18 m technology • Test prototype chip, evaluate and improve

  4. Milestones • 1st Chip design, synthesis 12/01/2000 • Chip fabrication 02/05/2001 • Chip testing 04/06/2001 1st report • 2nd chip design, synthesis 06/08/2001 2nd report, chip • Chip fabrication 08/10/2001 • Chip testing 10/12/2001 3rd report • Project presentation 11/30/2001 Final report, chip

  5. High speed ADC applications • Wideband RF, baseband RF, and IF signal • digitization • Wireless point to point system • Local multi-point distribution service • Wireless local loop • Computer network, universal adaptor • Radar/communications

  6. TIQ based ADC • Flash ADC • TIQ: Threshold Inverter Quantization • Comparator • Inverter comparator

  7. Flash ADC Vref V1 – + Vin R V2 V1 – + R D1 D2 V3 V2 D3 – + R V3 Dk – + R Vn Vn Thermometer code to binary encoder Resistor ladder circuit

  8. gain booster V1 Vin gain booster V2 D1 D2 gain booster D3 V3 Dk gain booster circuit gain booster Vn Thermometer code to binary encoder TIQ based ADC

  9. _ + Vin Vout Vin Vm Vout Vr Vout Vout Vr Vin Vm Vin TIQ Comparator DIFFERENTIAL INPUT VOLTAGE COMPARATOR INVERTER Vr is provided by a voltage references source, External to the voltage comparator Vm is an internal parameter of an inverter, fixed by the transistor sizes

  10. Advantages of TIQ based ADC • High speed • Less area • No resistor ladder and reference voltages • No capacitor switching • Future ready • Scale down • Low supply voltage • Standard digital logic technology • Ideal for SOC

  11. Intel’s 70-nm process takes gate to 30-nm length Manufacturing is slated for 2005  Source : EE TIMES 12/11/2000

  12. Challenges of TIQ based ADC • Process parameter variation • Single ended input

  13. Simulation results • 6bit at 1000 MSPS • 8bit at 500 MSPS • Layout area • Power • Process parameter variation

  14. Layout: 6-bit TIQ ADC

  15. 6-bit 1 GS/s

  16. 8-bit 500 MS/s

  17. Simulation results

  18. Process variation

  19. Innovation challenges • 2 GSPS with 0.18um CMOS • Custom layout CAD tool • 10bit and 12bit ADC • Low power • Dynamic calibration • Offset • Gain • Temperature • Power supply voltage • Process parameter variation

  20. Summary • High speed ADC for RF • ADC core - 6bit and 8bit design • prototype chips (silicon test) • 0.25 m (or 0.18 m) • CMOS digital logic technology • Future ready • Dynamic calibration

More Related