ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits

1. ECE 697B (667)Spring 2006Synthesis and Verificationof Digital Circuits Scheduling Algorithms Analytical approach - ILP

2. Scheduling – a Combinatorial Optimization Problem • NP-complete Problem • Optimal solutions for special cases and ILP • Integer linear program (ILP) • Branch and bound • Heuristics • iterative Improvements, constructive • Various versions of the problem • Unconstrained minimum latency • Resource-constrained minimum latency • Timing constrained minimum latency • Latency-constrained minimum resources • If all resources are identical, problem is reduced to multiprocessor scheduling (Hu’s algorithm) • Minimum latency multiprocessor problem is intractable under resource constraint ECE 667 - Synthesis & Verification - Lecture 3

3. Integer Linear Programming • Given: integer-valued matrixAm x n vectors:B = ( b1, b2, … , bm ) and C = ( c1, c2, … , cn ) • Minimize: CT X subject to: A XB X = ( x1, x2, … , xn ) is an integer-valued vector ECE 667 - Synthesis & Verification - Lecture 3

4. Integer Linear Programming - Scheduling • Problem (simple version) Assumption: identical computations, each computation takes one cycle For a set of (dependent) computations {v1,v2,...,vn}, find the minimumnumberof units needed to complete the execution inkcontrol steps (MR-LCS problem) • Integer Linear Programming (ILP): • Lety0be an integer variable (# units to be minimized) • for each control stepl =1, …, k, define variablexilas xil = 1, if computationvi is executed in thel-thcontrol step xil= 0, otherwise • define variable yl (number of units in control stepl ) yl = x1l + x2l + ... + xnl =ixil ECE 667 - Synthesis & Verification - Lecture 3

5. ILP Scheduling • For each precedence relation: • If vj has to be executed aftervi- introduce dependency constraint: xj1 + 2 xj2+ ... + k xjkxi1 + 2 xi2 + ... + k xik+ d(i) ( for unit delay, d(i)= 1) Minimize:y0 Subject to: xj1+ xj2+ ...+ xjk= 1for allj = 1,…, n (computations) yl  y0for alll= 1,…, k(steps) • 1st constraint: each computation vi can start only once: • xil= 1 for only one value ofl (control step) • Meaning of y0: upper bound on the number of units, to be minimized ECE 667 - Synthesis & Verification - Lecture 3

6. v1 v2 v3 v4 v5 v6 Example 1 - Formulation n = 6 computations k = 3 control steps • Execution constraints: • xi1 + xi2 + xi3 = 1fori = 1,…, 6 • Resource constraints: • yl = x1l + x2l + x3l+ x4l + x5l + x6lfor l = 1,…, 3 (steps) • Dependency constraints:e.g.v4executes afterv1 • x41 + 2x42+ 3x43 x11 + 2x12 + 3x13 +1 • . . . . . . . etc. ECE 667 - Synthesis & Verification - Lecture 3

7. v1 v2 v4 v3 v6 v5 Example 1 - Solution • Minimize: y0 • Subject to: yly0for alll= 1,…, 3 Dependency constraints … Execution constraints … • One solution: y0 = 2 x11 = 1, x21 = 1, x32 = 1, x42 = 1, x53 = 1, x63 = 1. all otherxil= 0 ECE 667 - Synthesis & Verification - Lecture 3

8. l=tiL lxil =  xil l=tiS ILP Model of Scheduling • Binary decision variables xil xil = 1 if operation vistarts in stepl i = 0, 1, …, n (operations) l= 1, 2, … +1 (steps, with limit  ) • Start time is unique: Start time for vi: Note: where: t iS = time of operation I computed withASAP t iL = time of operation I computed withALAP ECE 667 - Synthesis & Verification - Lecture 3

9. ILP Model of Scheduling (contd.) • Precedence relationships must be satisfied • Resource bounds must be met • let upper bound on number of resources of type k be ak ECE 667 - Synthesis & Verification - Lecture 3

10. Minimum-latency Scheduling under Resource-constraints • Let tbe the vector whose entries are start times • Formal ILP model ECE 667 - Synthesis & Verification - Lecture 3

11. Example 2 – Multiple Resources • Two types of resources • Multiplier • ALU • Adder • Subtraction • Comparison • Both take 1 cycle of execution time ECE 667 - Synthesis & Verification - Lecture 3

12. Example 2 (contd.) • Heuristic (list scheduling) gives latency = 4 steps • Use ALAP and ASAP (with no resource constraints) to get bounds on start times • ASAP matches latency of heuristic • (so heuristic is optimum) • Constraints? ECE 667 - Synthesis & Verification - Lecture 3

13. l=tiL lxil =  xil l=tiS Example 2 (contd.) • Start time must be unique Recall: where: t iS = time of operation i computed with ASAP t iL = time of operation i computed with ALAP ECE 667 - Synthesis & Verification - Lecture 3

14. Example 2 (contd.) • Precedence constraints • Note: only non-trivial ones listed (those with more than one possible start time for at least one operation) ECE 667 - Synthesis & Verification - Lecture 3

15. Example 2 (contd.) • Resource constraints MULT a1=2 ALU a2=2 ECE 667 - Synthesis & Verification - Lecture 3

16. Example 2 (contd.) • Considerc = [0, 0, …, 1]T • Minimum latency schedule • since sink has no mobility (xn,5 = 1), any feasible schedule is optimum • Considerc = [1, 1, …, 1] T • finds earliest start times for all operations  i  l • or equivalently: ECE 667 - Synthesis & Verification - Lecture 3

17. Example Solution 2: Optimum Schedule Under Resource Constraint ECE 667 - Synthesis & Verification - Lecture 3

18. Example 3 • Assume multiplier costs 5 units of area, and ALU costs 1 unit of area • Same uniqueness and sequencing constraints as before • Resource constraints are in terms of unknown variables a1 and a2 • a1 = number of multipliers • a2 = number of ALUs (add/sub) ECE 667 - Synthesis & Verification - Lecture 3

19. Example 3 (contd.) • Resource constraints MULT ALU ECE 667 - Synthesis & Verification - Lecture 3

20. Example 3 - Solution • MinimizecTa= 5.a1 + 1.a2 • Solution with cost = 12 ECE 667 - Synthesis & Verification - Lecture 3

21. Precedence-constrained Multiprocessor Scheduling • All operations performed by the same type of resource • intractable problem; even if operations have unit delay ECE 667 - Synthesis & Verification - Lecture 3