1. Glitches Discussion D2.7 Example 10

2. Source of Glitches 1 1 1 1 0 0 1

3. Source of Glitches 1 1 1 1 1 0 1

4. Source of Glitches 1 1 0 1 1 1 1

5. Source of Glitches 1 0 0 1 1 1 1

6. Source of Glitches 1 0 0 1 1 1 1

7. Source of Glitches 1 0 0 1 0 1 1

8. Source of Glitches 1 0 1 1 0 0 1

9. Source of Glitches 1 1 1 0 0 0 1

10. Source of Glitches 1 1 1 1 0 0 1

11. -- Example 10: A 2-to-1 MUX with glitch library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux_glitch is port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC ); end mux_glitch; architecture mux_glitch of mux_glitch is signal nots, c, d: STD_LOGIC; begin nots <= not s after 2ns; c <= nots and a after 2ns; d <= s and b after 2ns; y <= c or d after 2ns; end mux_glitch;

12. Aldec Active-HDL Simulation

13. Eliminating Glitches 1 1 Add another AND gate 1 1 0 0 1

14. -- Example 10: A 2-to-1 MUX with glitch removed library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux_glitchR is port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC ); end mux_glitchR; architecture mux_glitchR of mux_glitchR is signal nots, c, d, e: STD_LOGIC; begin nots <= not s after 2ns; c <= nots and a after 2ns; d <= s and b after 2ns; e <= a and b after 2ns; y <= c or d or e after 2ns; end mux_glitchR;

15. Aldec Active-HDL Simulation