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Computer Organization Lecture 25

Computer Organization Lecture 25. Virtual memory Page replacement Translation lookaside buffer (TLB). Memory design goals. Unlimited memory size No upper bound on memory addresses Not practical or possible: cost, implementation Infinite memory bandwidth Zero latency memory accesses

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Computer Organization Lecture 25

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  1. Computer OrganizationLecture 25 Virtual memory Page replacement Translation lookaside buffer (TLB) University of Portland School of Engineering

  2. Memory design goals • Unlimited memory size • No upper bound on memory addresses • Not practical or possible: cost, implementation • Infinite memory bandwidth • Zero latency memory accesses • Not practical or possible: cost, laws of physics • Memory hierarchy can approximate goals University of Portland School of Engineering

  3. Virtual memory • Programmer sees extremely large memory • Memory divided into pages (1K, 4K, 8K, etc.) • Some pages exist in memory, rest on hard drive • Pages in use cached in memory • Provides good performance-cost tradeoff • Requires table to map memory pages to disk (cylinder, head, sector) • Memory access either hit or miss page University of Portland School of Engineering

  4. Virtual and physical memory Memory-resident frames Page table translates virtual-to-physical Disk-resident pages University of Portland School of Engineering

  5. OS demand paging • Bring a page into memory only when it is needed (on first request) • Less I/O needed, less memory needed • Faster response, better performance • OS (pager) must first check page attributes • Illegal reference  error condition • Not-in-memory  bring into memory • Memory resident  continue University of Portland School of Engineering

  6. Page fault steps • First reference to page: traps/interrupts to OS  page fault (miss) • OS looks at page table • Invalid reference  abort, error condition • Page not in memory • Get empty frame from free frame list • Copy (write) page into frame • Update page table, set valid bit = 1 • Restart instruction University of Portland School of Engineering

  7. Free frames list After allocation Before allocation University of Portland School of Engineering

  8. What if free frame list is empty? • Reason • Too many users • Too many programs • Too much data, etc. • Solution • Find a frame to evict (create space) • May require write-back to disk University of Portland School of Engineering

  9. Page Replacement • Find the location of the desired page on disk • Find a free frame (algorithm) • If there is a free frame, use it • If there is no free frame, use a page replacement algorithm to select a victim frame • Evict victim frame: write to disk if modified (dirty), write-back University of Portland School of Engineering

  10. Page Replacement, continued. • Read the desired page into the (newly) free frame • Update page table • Update frame table • Restart the process (instruction) University of Portland School of Engineering

  11. DMA write DMA read Page replacement steps University of Portland School of Engineering

  12. Page replacement algorithm? (Which page to evict) University of Portland School of Engineering

  13. Paging memory performance • Similar to cache performance • Hit: memory page is resident • Miss: memory page on disk only • Access time University of Portland School of Engineering

  14. Find the access time? Find an expression for the average access time Tave of a memory-hard disk hierarchy? Assume the page rate (hit) is p, memory access time is m, the I/O bus bandwidth is b, the size of a page is s bytes, a page is found dirty (modified) with probability d, and the free page list is always empty (memory full). University of Portland School of Engineering

  15. Find the access time? Continued. University of Portland School of Engineering

  16. Problems with paging • Page table can become enormous • Several OS solutions • Hashing function, inverted page table • Each memory access requires page table access (another memory access) • Cache the page table • Translation lookaside buffer (TLB) University of Portland School of Engineering

  17. TLB • Purpose: hardware speed up for page table access • What it is: small, fast cache of recently used page table entries • Accesses • Hit: page table value is cached (fast) • Miss: page table value not cached, must read it from memory University of Portland School of Engineering

  18. Pentium 4 execution engine University of Portland School of Engineering

  19. Find the effective memory access? TLB = 20 ns, mem = 100 ns, hit = 0.8 University of Portland School of Engineering

  20. University of Portland School of Engineering

  21. Page replacement algorithm? (Which page to evict) • Least recently used (LRU) • First in, first out (FIFO) • Optimal: lowest page fault rate • Random University of Portland School of Engineering

  22. Find the effective memory access? TLB = 20 ns, mem = 100 ns, hit = 0.8 University of Portland School of Engineering

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