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Computer System Overview

Computer System Overview. Chapter 1 Review of basic hardware concepts . The OS and the Hardware. An Operating System makes the computing power available to users by controlling the hardware Let us review the aspects of computer hardware which are important for the OS. Basic Components.

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Computer System Overview

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  1. Computer System Overview Chapter 1 Review of basic hardware concepts

  2. The OS and the Hardware • An Operating System makes the computing power available to users by controlling the hardware • Let us review the aspects of computer hardware which are important for the OS Chapter 1

  3. Basic Components • Processor (CPU) • Main Memory (RAM, primary memory) • holds data and code • I/O modules (I/O controllers, I/O channels, I/O processors...) • hardware (with registers called I/O ports) that moves data between CPU and peripherals like: • secondary memory devices (ex: hard disks) • keyboard, display... • communications equipment • System interconnection (buses, channels) • communication among processors, memory, and I/O modules Chapter 1

  4. Main Components PSW PSW = Program Status Word Chapter 1

  5. CPU Registers (fast memory on CPU) • Control & Status Registers • generally not available to user programs • some used by CPU to control its operation • some used by OS to control program execution • User-visible Registers • available to system (OS) and user programs • only visible when using machine and assembly languages • hold data, addresses, and some condition codes Chapter 1

  6. Examples of Control & Status Registers • Program Counter (PC) • Contains the address of the next instruction to be fetched • Instruction Register (IR) • Contains the instruction most recently fetched • Program Status Word (PSW) • A register or group of registers containing: • condition codes and status info bits • Interrupt enable/disable bit • Supervisor(OS)/user mode bit Chapter 1

  7. User-Visible Registers • Data Registers • dedicated to contain data information. Can have many functions, depending on the structure of the machine code and on programmer’s decisions (accumulator, etc.) • Address Registers • contain memory address of data and instructions • may contain a portion of an address that is used to calculate the complete address Chapter 1

  8. User-Visible Address Registers • Index/Offset • involves adding an index to a base value to get an address • Segment pointer • when address space is divided into segments, memory is referenced by a segment number and an offset • Stack pointer • points to top of stack • for subroutine entry/exit (Appendix 1B) Chapter 1

  9. User-Visible Registers • Condition Codes or Flags • Bits set by the processor hardware as a result of operations • Can be set by a program but not changed directly • Examples • sign flag • zero flag • overflow flag Chapter 1

  10. The Basic Instruction Cycle • The CPU fetches the next instruction (with operands) from memory. • Then the CPU executes the instruction • Program counter (PC) holds address of the instruction to be fetched next • Program counter is automatically incremented after each fetch Chapter 1

  11. In the simplest machine organization, CPU must wait for I/O completion • WRITE transfers control to the printer driver (I/O pgm) • I/O pgm prepares I/O module for printing (4) • CPU has to WAIT for I/O command to complete • I/O pgm finishes and reports status of operation • CPU wastes much time waiting Chapter 1

  12. Interrupts • Invented to allow overlap of input and processing times • CPU launches I/O, returns to processing and then gets interrupted when I/O completed • The I/O module sends an interrupt request on the control bus • Then CPU transfers control to an Interrupt Handler Routine (normally part of the OS) Chapter 1

  13. Instruction Cycle with Interrupts • If interrupts are enabled, CPU checks for interrupts after each instruction • If no interrupts, then fetch the next instruction for the current program • If an interrupt is pending, then suspend execution of the current program, and execute the interrupt handler (in the OS) • Note: disabling interrupts should be done only when really necessary, because it can cause loss of information. Chapter 1

  14. Interrupt Handling: similar to subroutine call but it is not controlled by user program User program must restart as if there was no interruption Chapter 1

  15. Interrupt Handler • Is a program that determines nature of the interrupt and performs whatever actions are needed • Upon interrupt, control is transferred to this program • This is done by transferring control to a memory location that is determined by the type of interruption: interrupt vector • Control must be transferred back to the interrupted program so that it can be resumed from the point of interruption • The point of interruption can be anywhere in the program (except where interrupt inhibited). • Thus: must save the state of the process (content of PC + PSW + registers + ...) Chapter 1

  16. Simple Interrupt Processing Restore Process Control Block Save Process Control Block Chapter 1

  17. Interrupts improve CPU usage • I/O pgm prepares the I/O module and issues the I/O command (eg: to printer) • Control returns to user pgm • User code gets executed during I/O operation: no waiting • User pgm gets interrupted (x) when I/O operation is done • Control goes to interrupt handler to check status of I/O module and perform necessary processing • Execution of user code resumes Chapter 1

  18. Interrupts: terminology • Not normalized, but it is a good idea to distinguish between: • traps or exceptions: caused by the pgm as it executes • division by 0 • illegal access • system calls... • interruptions: caused by independent events: • end I/O • timers • faults: term used esp. in connection with paging and segmentation • But the hardware mechanisms are similar for all Chapter 1

  19. Multiple interrupts: sequential order • Disable interrupts during an interrupt • Interrupts remain pending until the processor enables interrupts • After interrupt handler routine completes, the processor checks for additional interrupts Chapter 1

  20. Multiple Interrupts: priorities • Higher priority interrupts cause lower-priority interrupts to wait • Causes a lower-priority interrupt handler to be interrupted • Example: when input arrives from communication line, it needs to be absorbed quickly to avoid retransmission • This requires a stack mechanism to save registers, etc. Chapter 1

  21. `Long` I/O • Normally I/O are very long with respect to I/O processing • In this case, the program and the CPU will have to wait even if there is concurrency between I/O and CPU processing Chapter 1

  22. Multiprogramming • Allows to achieve better use of I/O overlap times. • When a program reads a value on a I/O device it will need to wait s long time for the I/O operation to complete. • It can be difficult to use this waiting time. • So interrupts are mostly effective when a single CPU is shared among several concurrently active processes. • The CPU can then switch to execute another program when a program waits for the result of the read operation. Chapter 1

  23. I/O communication techniques • 3 techniques are possible for I/O operation (increasing sophistication) • Programmed I/O • Does not use interrupts: • CPU has to wait for completion of each I/O operation • Interrupt-driven I/O: CPU asks for I/O then continues • CPU can execute during I/O operation: • it gets interrupted when I/O operation is done • still, it has to transfer bytes from I/O to memory, so there is a slowdown (cycle stealing). • Direct Memory Access (DMA) • A block of data is transferred directly from/to memory without going through CPU¸ • But CPU will still have to be interrupted Chapter 1

  24. Programmed I/O • There is no interrupt, CPU is kept busy checking status of I/O module (polling orbusy waiting). • No I/O overlap is possible • Only used in very simple machines. Chapter 1

  25. Interrupt-Driven I/O • CPU starts I/O then goes to other work • Processor is interrupted when I/O module ready to exchange data • No needless waiting • However every word read or written still passes through the CPU (cycle stealing) • CPU performance is affected by I/O Chapter 1

  26. Direct Memory Access • CPU issues request to a DMA module (separate module or incorporated into I/O module) • DMA module transfers a block of data directly to or from memory (without going through CPU) • An interrupt is sent when the task is complete • The CPU is only involved at the beginning and end of the transfer • The CPU is completely free to perform other tasks during data transfer Chapter 1

  27. MEMORY CHANNELS CPU Without DMA MEMORY CHANNELS CPU Direct Memory Access Chapter 1

  28. Cycle stealing • In general, when CPU and I/O operations must share physical components (bus, CPU, memory), I/O functions by occasionally stealing cycles from these components • When I/Os must pass through CPU (technique 2), the CPU must find the time to transfer bytes between I/O units and memory while it executes a program • Even in the case of DMA CPU and I/O share the memory, so the CPU can be delayed in its accesses to memory. Chapter 1

  29. Memory Hierarchy Cheaper Larger capacity Slower Registers Cache Main Memory Magnetic Disc Smaller frequency of access Removable Media Chapter 1

  30. Cache Memory • Small cache of expensive but very fast memory interacting with slower but much larger memory • Invisible to OS and user programs but interact with other memory management hardware • Processor first checks if word referenced to is in cache • If not found in cache, a block of memory containing the word is moved to the cache Chapter 1

  31. Chapter 1

  32. The Hit Ratio • Hit ratio = fraction of access where data is in cache • T1 = access time for fast memory • T2 = access time for slow memory • T2 >> T1 • When hit ratio is close to 1 the average access time is close to T1 Chapter 1

  33. Locality of reference: a very important property of most programs • Memory references for both instruction and data tend to cluster over a long period of time. • Example: once a loop is entered, there is frequent access to a small set of instructions. Similarly, data is usually accessed in sequence. • Hence: once a word gets referenced, it is likely that nearby words will get referenced often in the near future. • Thus, the hit ratio will be close to 1 even for a small cache. Chapter 1

  34. Disk Cache (same principles) • A portion of main memory used as a buffer to temporarily to hold data for the disk • Locality of reference also applies here: once a record gets referenced, it is likely that nearby records will get referenced often in the near future. • If a record referenced is not in the disk cache, the sector containing the record is moved into the disk cache. Chapter 1

  35. Important concepts of Chapter 1 • Interrupts and how they work • 3 methods of I/O • simultaneity among I/O and CPU processing • memory hierarchy • cache memory • locality of reference Chapter 1

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