Sanjee Abeytunge Department of Physics and Astronomy Stony Brook University Stony Brook, New York.

1. Prototype Design of the Front End Module (FEM) for the Silicon Pixel Vertex Tracker in the PHENIX Experiment Sanjee Abeytunge Department of Physics and Astronomy Stony Brook University Stony Brook, New York. September 7, 2004 Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

2. Topics of Discussion • ALICE1LHCB readout chip and its format • Data Simulator • Drift Chamber FEM and the Interface board • Test Setup • Results • Outlook • Conclusions and Issues Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

3. ALICE1LHCB readout chip • Each chip reads 32 x 256 pixels • Registers “hit” pixels; each pixel is a bit. • Readout 32 x 256 bits at 10 MHz • 8 chips (½ ladder ) are controlled and read out by the Pilot MCM • Upon trigger Pilot MCM initiates readout of 8 chips sequentially on a 32-bit bus • GOL allows transmission of 16-bit data @ 40 MHz • GOL transmits via G-Link Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

4. ALICE1LHCB Format – according to the document available • 100 ns long frames • Each frame – 2 control words, 2 data words (16-bit wide) • When there is no data – Idle frames ( 2 control words, 2 no data words) • Bit specification identifies the event #, chip, first_word, last_word, fast_or etc. Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

5. ALICE Data Transmission Principle Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

6. Bit Configuration for Cycles & Frames cav dav dav In every frame Only Event Word frame “hit” Word frame Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

7. Synchronizing Pilot MCM to the Link Receiver • Pilot MCM near the detector; Link receiver in the control room; needs synchronization • Link receiver must identify the different cycles • Two step process to synchronize: 1) Synch Pilot MCM to the Link Receiver 2) Synch Link receiver to the proper data block Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

8. Synch Pilot MCM to the Link Receiver • Pilot near the detector; Receiver near the control room • Identify slots with two control bits available in the G-Link protocol • These two bits provide following signals: cav – Active when a control word available Active during slot 0 dav – Active when a data word available Active during slot 1a and slot 1b Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

9. Synch Link receiver to the proper data block • Identify the first_word signal : Activate bit 28 & 29 during slot0-cycle0 • Identify the last_word signal : Activate bit 26 & 27 during slot0-cycle0 • fast_or signal: Activated if at least one pixel has been “hit” Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

10. Data Simulator (DS) External Trigger • Use National Instrument’s NI-5411 pattern generator modules • Use two modules: • One to simulate the “hit” data • One to simulate the cav & dav signals • Use LabVIEW to talk to the generators • Provide clock and trigger from the interface board FEM-DS • Use “stepped trigger” mode External Clock Digital Data Out SHC50-68 cable Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

11. NI 5411 Pattern Gen 1 16 bits LabVIEW Clock / Trigger Clock / Trigger PXI 8175 Controller NI 5411 Pattern Gen 1 16 bits FEM-DS Board Data Simulator and FEM-DS flow diagram Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

12. Our Input File in Frame format 256 32-bit words 32-bit word DATA 2 CONTROL F I RSTWORD CONTROL WORD EVENT DATA EVENT DATA CONTROL WORD CONTROL WORD DATA 1 CONTROL WORD CONTROL WORD DATA 3 DATA 4 CONTROL LAST WORD CONTROL WORD DATA 5 1 1 DATA 5 1 2 CONTROL WORD CONTROL WORD NO DATA NO DATA CONTROL WORD CONTROL WORD NO DATA NO DATA CONTROL WORD CONTROL WORD NO DATA NO DATA 16 bits Event Word Frame Last Word Frame Includes real data from the last two data words 3 Idle Frames In stepped trigger mode 1st 8 16-bit words are repeated until another trigger is received First “hit” Word Frame Includes real data from the first two data words Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

13. Bits and Data Input File • It’s a 16-bit word • Use the bit specs used by ALICE1LHCB • A bit ‘on’ is 1, and a bit ‘off’ is 0 • Convert the binary number to decimal number • Program it into the input file Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

14. Input Data File and the Input cav/dav File • Remember we use the 2nd pattern generator for cav/dav – 16 bits available • Only two bits are needed – one for cav and another for dav • Use bit 1 (10) for dav and bit 2 (100)for cav • This means, program 2 for dav and 4 for cav for every Data Word & Control Word Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

15. Drift Chamber FEM and the Interface board • Use DC FEM to connect to the PHENIX DAQ • Use an interface board to translate data from the data simulator into a format the DC FEM expects Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

16. Block Diagram of the DC FEM Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

17. FEM-DS Interface Board • Purpose: • Separate Control Words and “hit” Data Words. • Buffer data coming in at 20 MHZ and send out at 40 MHz. • Receives timing, control and reset signals from the FEM • Transmits trigger and clock to the DS • Receives input data ( “hit” Data and cav/dav) from the DS • Transmits “hit” Data to the FEM Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

18. Futurebus Connectors Power In +5V FEM-DS Board JTAG Conector Power-On Reset +3.3V Vol Regulator EE-Prom Fuse Low Profile Connectors FPGA Jumper LVPECL to LVTTL converter FEM or GTM Clk & Trig Selector +2.5V Vol Regulator Limo Conectors 50 W Line Driver Trigger Out BNC Connectors Clock Out BNC Connectors General I/O Connector Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

19. Control Signals • Signals to the FEM_DS: • 40 MHz clock (from FEM). • Collect_Data signal (from FEM) tells the FEM-DS to tell the generator to initiate pattern generation. • Read_Data signal (from FEM) tells the FEM-DS to start sending the data. • Signals from the FEM-DS: • Trigger (Collect_Data) (to DS) • 40MHz clock (to DS) Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

20. Test Setup • Includes key components of the PHENIX readout system – FEM, DCM & GTM • FEM-DS interface board • Data simulator Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

21. Data Simulator (DS) Data_Trigger ( Collect_Data) 256 16-bit Data Frames + 3 16-bit Idle Frames + 1 16-bit Event Frame = 1040 Words NI5411 Module 2 520 16-bit cav Words + 520 16-bit dav Words = 1040 Words NI5411 Module 1 PC LabVIEW Interface PXI 8175 Controller 40 MHz Clock FEM 16 bit Data Words 2 bits for cav / dav FEM-DS Board LOGIC ANALYZER 514 word data stream cav, dav and fastor can be used for timing analysis of Data Words 40 MHz Clock GTM PC Collect_Data G-Link Tranmitter 1040 cav/davWords + 526 control Words 514 Data Words Read_Data 16 bit Data Words + 2 bits for first / last words Clock/Trig, Readout Control, Mode-bits etc. Initialization/ Status G-Link Receiver header + 514 Data Words + trailer G-Link Tranmitter ARCNet Data-flow FPGA G-Link Receiver FIFO FEM Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

22. Test Setup Data_Trig / Clock Collect_Data / Clock Read Data cav/dav Data Data Data Simulator FEM-DS Board FEM “hit” Data ENDAT / Clock “hit” Data Logic Analyzer GTM Simulator Board DCM Simulator Board Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

23. Measurement for full readout cycle Fill frames for synch Data at DCM CollectData Read_Data 30.06 µs Time needed to read 514 words Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

24. First “hit” Data Words Event Numbers and 1st word indication Beam Clk Counter Data 1 Data 2 Data 3 Data 4 Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

25. Data 511 and Last word indication User Word Data 512 and Last word indication User Word all zeros User Word Parity Word Status End of the transmission Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

26. Outlook • Bring chip test board and readout cards to SB • Learn to operate the system • Develop the FEM prototype Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

27. Issues • Optical Rx/Tx from/to detector needs clarification due to lack of documentation. Should be resolved when chip & readout system available. • G-Link replacement must have higher bandwidth • 2 chips: 2 x (2 x 256) = 1024 16-bit words • ½ ladder: 2chips x 4 = 4096 16-bit words • @ 40 MHz approximate readout time 120 µs • Need to transfer at a higher rate to avoid bottle neck • Full ladder readout time ~ 240 µs • Approximately factor of 5 increase in transmission bandwidth • ArcNet – PHENIX decision Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

28. Conclusions • 256 pairs of 16-bit data words were read out in ~ 30 µs • Equivalent to reading out 256 32-bit data words from one ALICE1LHCB chip • Next phase of the prototype design of the FEM would be to readout 8 ALICE1LHCB chips, or ½ ladder within the time restrictions set by PHENIX Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York

29. Acknowledgements • Many thanks to • Axel Drees • Chuck Pancake Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York