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ECE 681 VLSI Design Automation

ECE 681 VLSI Design Automation

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ECE 681 VLSI Design Automation

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  1. ECE 681VLSI Design Automation Khurram Kazi Thanks to Automation press THE button outcomes the Chip !!! Reality or Myth

  2. Course Outline • Overview of ASIC design flow • Writing VHDL for Synthesis • Behavioral Modeling (Test Bench Development in VHDL) • How to Constrain and Optimize the Design in Synthesis • Introduction to Specman ‘e’; Language for verification • Self Checking Design Verification Concepts • Overview of Verilog (another HDL) with Synthesis in mind • Gate Level Verification • Formal Checking • Static Timing Analysis.

  3. Grading Policy • Homework 20% • 2 Midterms 40% • Final Project 40% • Homework and Final Projects can be customized to your field of specialization, may it be in Data Networking, Cryptography, Specialized Arithmetic Operations, Video Compression etc.

  4. Do’s and Don’ts for the Final Project • Any off the shelf general purpose microprocessor or any other circuit taken from the publicly available information base. • Come up with your own functional idea and Implement it. Be creative! Have a system’s perspective and see how your ASIC fits in the system.

  5. How much collaboration is acceptable • Since time will be short, I would encourage you to help out your fellow students with the “Usage of the Tools” and not the Design. Informing me of the help received is strongly encouraged. • Helping with Tools and class participation will be rewarded in the final grade.

  6. Overview of Some of the steps in an ASIC flow

  7. RTL Block Synthesis* *Simplified design flow

  8. Insert Test Structure (Internal Scan and JTAG)* *Simplified design flow

  9. Insert Test Structure (Internal Scan and JTAG)* *Simplified design flow

  10. Insert I/O Pads* *Simplified design flow

  11. ASIC Floorplan* *Simplified design flow

  12. Getting ASIC Ready for Handoff* *Simplified design flow

  13. Where to Start in the ASIC Process! • Begin with ASIC Specification (most likely by the time you are done the Final Spec. will be quite different) • Based on performance requirements define operating frequencies, I/O pad types, operating conditions, verification and test requirements to ensure error free design and manufacturability

  14. Overview of Synthesizable VHDL • Library and Library Declarations • Entity Declaration • Architecture • Configuration

  15. Overview of Synthesizable VHDL • Package contains commonly used declarations • Constants maybe defined here • Enumerated data types (SFD, SA, DA) • Combinatorial functions (performing a decode function; returns single value) • Procedures (can return multiple values) • Component declarations

  16. Overview of Synthesizable VHDL • Entity • Defines the component name, its inputs and outputs (I/Os) and related declarations. • Can use same Entity for different architecture to study various design trade offs. • Use std_logic and std_logic_vector(n downto 0): they are synthesis friendly. • Avoid enumerated type of I/Os. • Avoid using port type buffer or bidir (unless have to)

  17. Overview of Synthesizable VHDL • Architecture • Defines the functionality of the design • Normally consists of processes and concurrent signal assignments • Synchronous and/or combinatorial logic can be inferred from the way functionality is defined in the Processes. • Avoid nested loops • Avoid generate statements with large indices Always think hardware when developing code!

  18. Some useful starting practices • Organize Your Design Workspace • Define naming convention (especially if multiple designers are on the project • Completely Specify Sensitivity Lists • Try to separate combinatorial logic from sequential logic

  19. Separation of Combinatorial and Sequential Logic

  20. Synthesis of “if – then – elsif” statement

  21. Case statement Synthesis

  22. What is synthesized from this Code? Missing else Otherwise a latch is inferred Process (A, B) begin if (A = ‘1’) then Q <= B; end if; end process; // there are 2 outputs, Q and Z Process (c) begin case C is when ‘0’ => Q <= ‘1’; Z <= ‘0’; when others => Q <= ‘0’; end case; end process; Missing Z output Otherwise a latch is inferred

  23. for loop synthesis Example(0) <= a(0) and b(5); Example(1) <= a(1) and b(4); Example(2) <= a(2) and b(3); Example(3) <= a(3) and b(2); Example(4) <= a(4) and b(1); Example(5) <= a(5) and b(0); Process (a,b) begin for i in 0 to 5 loop example (i) <= a(i) and b(5-i); end loop; end process; for loops are “unrolled” and then synthesized.

  24. Example of SONET Framing block in a framer ASIC 1 2 3 4 5 ………….. ………. 90th byte A1 A2 1 2 3 4 5 6 7 8 9 A1 = hexF6, A2 = hex28; is the framing pattern used in SONET networks; Order or transmission is F6 (11110110) msb transmitted first.

  25. Frame Acquisition in SONET (STS-1) • Each frame consists of 810 bytes. The first 2 bytes are A1 and A2. These two bytes have same fixed patter. Hence used for acquiring framing, i.e. byte boundary is defined. It takes 2 frames to go in sync. • Once in frame, framer keeps monitoring A1A2 bytes. If 2 contiguous wrong patterns are detected for A1A2 -> errored frame is implied • 4 contiguous A1A2 wrong patterns -> severely errored frame • 24 contiguous A1A2 wrong patterns -> out frame state is declared. Respective alarms are generated.

  26. What will it take to design a SONET framer (simple version) • Shift in the data in a 16 bit long shift register and match the F628 pattern. • Once that pattern is detected, load an octet (byte) counter with a value of 2 (corresponds to the 3rd byte in the SONET frame) • Every time counter is 0 and 1, compare the bytes with F628 pattern to ensure framing is maintained.

  27. Assignment 1 • Design a SONET framer. Based on A1 and A2 pattern, design a counter that counts 0-809 bytes. There should be a bit counter that maintains the byte boundary. The bit counter is set to a value of 0 the next cycle the A2 byte pattern is detected. From then on, the bit counter is modulo 8 counter and the byte counter is a modulo 810. Every time bit counter counts to 7, the next cycle the byte counter gets incremented. • In the design define states (header0, payload0, header1, payload1, header3, payload3 … header8, payload8). Header0 corresponds to when the byte counter is counting between 0-2, payload0 ->3-89, header1 ->90-92, payload1 -> 93-179 and so on till the counter wraps around. • Hints: Start your designs by writing code for 16 shift register. Every cycle do a check for the F628 pattern. The decode of that pattern should be used to preload your bit and byte counters. • Need to generate a test bench that generate SONET frame data. It can be a sequence of up counter with only two bytes to have the F628 pattern in the data stream. Make sure the rest of the bytes of the 810 byte frame do not have that pattern. Do not start the first two bytes of your test bench pattern generator with F628 pattern.