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Update on SP02 design by Victor Golovtsov & Lev Uvarov

Update on SP02 design by Victor Golovtsov & Lev Uvarov. Trigger Meeting at Rice August 2002. Outline. GTLP Backplane Termination FPGA Configuration Boundary Scan. GTLP Backplane Termination. Rephrasing the “Recommendation on GTLP bus Implementation”:

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Update on SP02 design by Victor Golovtsov & Lev Uvarov

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  1. Update on SP02 designby Victor Golovtsov & Lev Uvarov Trigger Meeting at Rice August 2002

  2. Outline • GTLP Backplane Termination • FPGA Configuration • Boundary Scan Victor Golovtsov, Lev Uvarov

  3. GTLP Backplane Termination • Rephrasing the “Recommendation on GTLP bus Implementation”: • As shown in fig below, Vref is set by an R/2R resistor network between VTT and GND. • The resistor network maintains balanced upper and lower noise margins for any termination voltage fluctuations. • So • Vref should be generated locally on each card • Since the termination network and VTT resides on the backplane, the card resistor network should take VTT from the BACKPLANE through a CCB connector pin. • SP02 design expects VTT to be available through B11 pin. Victor Golovtsov, Lev Uvarov

  4. FPGA Configuration Modes • SP02 carries 7 Virtex-II FPGAs on the main board plus 1 Virtex-II FPGA on the Mezzanine Card. Victor Golovtsov, Lev Uvarov

  5. Boundary Scan • Two tasks for boundary scan interface: • Testing the JTAG-compatible hardware for shorts and opens per IEEE 1149.1 (All Xilinx devices plus all GSI SRAMs, 65 devices total) • Configuring FPGAs per IEEE 1532 (All Xilinx device, 20 devices total) • Three options to port to a local JTAG chain (chains): • Header for Xilinx’ Parallel Cable IV (2 mm pitch) • National SCANSTA111 Enhanced SCAN Bridge (one per SP02, supports up to 3 local chains). Uses the VME64x T&Mbus, but requires Boundary Scan Master in a Crate. • National SCANSTA101 Boundary SCAN Master (one per SP02, supports just one local chain). Requires a fuse-based CPLD for an auxiliary VME interface in each SP02. • Third approach (with older 5V devices) has been successfully implemented in the first SP prototype. • Second approach has been implemented and tested by Nuno Vaz Cardoso and Jose Carlos Da Silva from HC group. Victor Golovtsov, Lev Uvarov

  6. Boundary Scan - continue • They ported the SCAN Master functionality in the HDL form in the CPLD, built the VME card, as well as several test cards that used SCANSTA111 devices. • They also built a GUI (wrapper) around National’s ScanEase software. • The software used by both approaches is just the same. It is National’s command line utility ScanEase (Rev.2.0). Building a wrapper is a user’s problem. • Needs to be mentioned here that both SCANSTA101 and SCANSTA111 are available either in silicon or in the HDL form. • In the HDL form, each occupies about 15K gates. • So, a big enough CPLD would carry both VME interface and SCANSTA functionality. • Alex M. already got in touch with Ken Filliter from National, who provides support for SCAN devices and SCANEASE software. Victor Golovtsov, Lev Uvarov

  7. Boundary Scan - continue • Second approach has been implemented already in SP02 design, counting on already existed Boundary Scan Controller design at CERN. ( they schedule to launch production of their board this fall, so they could have ordered extra boards). • But this may change if the third option finally prevails. • In this case the JTAG interface will be redone. Victor Golovtsov, Lev Uvarov

  8. Mezzanine Card • Mezzanine card interfaces, as well as its dimensions are fully determined • 6 Samtec FOLC/MOLC connectors carry 780 signals, 16 power and 84 ground pins. • The card can accept either XC2V4000 or XC2V6000 devices. • It is designed with auxiliary power and JTAG connectors to facilitate testing. • The card image can be found on the “SP02 layout” slide. Victor Golovtsov, Lev Uvarov

  9. SP02 Layout slide shows current status of the board. • What’s new: • Two stiffeners from both sides of Front FPGAs • Switchers added, one per Xilinx device, for debugging purpose. • Backplane connectors moved a little bit, to be closer to corresponding drivers/receivers • DDU FPGA jumped to the next package size (from fg256 to fg456) • Number of buffers added to segment long traces • JTAG port implementation seems to be the only unresolved issue. Victor Golovtsov, Lev Uvarov

  10. SP02 Board Layout DC-DC Converter Phi Global LUT Eta Global LUT Phi Local LUT EEPROM Stiffener Indicators FM RJ45 VME/CCB FPGA TLK2501 Transceiver From CCB Front FPGA To MS DDU FPGA PT LUT Main FPGA Optical Transceiver MB1-to-SP Mezzanine Card ME1-to-DT Victor Golovtsov, Lev Uvarov

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