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Lecture #41: Active devices

This lecture covers active circuits, digital logic, and CMOS transistors. Topics include load-line method, RC circuits, logic gate delay, amplifier modeling, nodal analysis with dependent sources, and amplifier analysis using the amplifier model.

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Lecture #41: Active devices

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  1. Lecture #41: Active devices • This week we will be reviewing the material learned during the course • Today: review • Active circuits • Digital logic • CMOS transistors EE 42 fall 2004 lecture 41

  2. I (ma) I + - Solution: I = 0.7mA, V = 1.4V 2V 4 V 2K 2 V (Volt) 5 Example of the Load-Line Method Lets hook our 2K resistor + 2V source circuit up to an LED (light-emitting diode), which is a very nonlinear element with the IV graph shown below. Again we draw the I-V graph of the 2V/2K circuit on the same axes as the graph of the LED. Note that we have to get the sign of the voltage and current correct!! At the point where the two graphs intersect, the voltages and the currents are equal, in other words we have the solution. LED + - LED EE 42 fall 2004 lecture 41

  3. input voltage time voltage output time Simplification for time behavior of RC Circuits Before any input change occurs we have a dc circuit problem (that is we can use dc circuit analysis to relate the output to the input). Long after the input change occurs things “settle down” …. Nothing is changing …. So again we have a dc circuit problem. We call the time period during which the output changes the transient We can predict a lot about the transient behavior from the pre- and post-transient dc solutions EE 42 fall 2004 lecture 41

  4. 5 Vin R Input node Output node Vout + Vout C Vin 0 time - 0 ground RC RESPONSE Example – Capacitor uncharged: Apply voltage step of 5 V • Clearly Vout starts out at 0V ( at t = 0+) and approaches 5V. • We know this because of the pre-transient dc solution (V=0) and post-transient dc solution (V=5V). So we know a lot about Vout during the transient - namely its initial value, its final value , and we know the general shape . EE 42 fall 2004 lecture 41

  5. Capacitance to Ground D Actual exponential voltage versus time. LOGIC GATE DELAY D Time delay D occurs between input and output: “computation” is not instantaneous Value of input at t = 0+ determines value of output at later time t = D F A B Logic State Input (A and B tied together) 1 0 t 0 Output (Ideal delayed step-function) 1 F t 0 0 EE 42 fall 2004 lecture 41

  6. Oscilloscope Probe Note B changes one gate delay after A switches Note that C changes two gate delays after A switches. Note that D changes three gate delays after A switches. t 2t 3t t SIGNAL DELAY: TIMING DIAGRAMS Show transitions of variables vs time B C A D Logic state 1 A t 0 0 B t t C t t 2t D EE 42 fall 2004 lecture 41

  7. AMPLIFIER SYMBOL AMPLIFIER MODEL Differential Amplifier Circuit Model in linear region V0 V+ + A AV1 Ri  V +  V0 depends only on input (V+  V-) + + V0 V1   EXAMPLE OF THE USE OF DEPENDENT SOURCE IN THE MODEL FOR AN AMPLIFIER See the utility of this: this Model when used correctly mimics the behavior of an amplifier but omits the complication of the many many transistors and other components. EE 42 fall 2004 lecture 41

  8. R5 R R V V V 1 3 a b c R 2 + ISS VAA R R +  4 6 A V  v c NODAL ANALYSIS WITH DEPENDENT SOURCES Example circuit: Voltage controlled voltage source in a branch Write down node equations for nodes a, b, and c. (Note that the voltage at the bottom of R2 is “known” so current flowing down from node a is (Va AvVc)/R2.) CONCLUSION: Standard nodal analysis works EE 42 fall 2004 lecture 41

  9. NODAL ANALYSIS WITH DEPENDENT SOURCES Finding Thévenin Equivalent Circuits with Dependent Sources Present Method 1: Use Voc and Isc as usual to find VT and RT (and IN as well) Method 2: To find RT by the “ohmmeter method” turn off only the independent sources; let the dependent sources just do their thing. EE 42 fall 2004 lecture 41

  10. NODAL ANALYSIS WITH DEPENDENT SOURCES Example : Find Thévenin equivalent of stuff in red box. R V V a c 3 R 2 ISS R + 6 A V  v cs With method 2 we first find open circuit voltage (VT) and then we “measure” input resistance with source ISS turned off. You verify the solution: EE 42 fall 2004 lecture 41

  11. RF RF RS RS VIN V- VIN V- +   A V0 V0 V+ + V+ AV1 - V1 + EXAMPLE: AMPLIFIER ANALYSIS USING THE AMPLIFIER MODEL WITH Ri = infinity: Assume the voltage between the inputs is zero, and then figure out if that is consistent, or if the amplifier will hit a rail. Method: We substitute the amplifier model for the amplifier, and perform standard nodal analysis solution: RIN = VO/VIN = EE 42 fall 2004 lecture 41

  12. Differential Amplifier Circuit Model in linear region V0 V+ + A AV1 Ri  V +  + + V1 V0 But if A ~ , is the output infinite? “Very high gain”   OP-AMPS AND COMPARATORS A very high-gain differential amplifier can function either in extremely linear fashion as an operational amplifier (by using negative feedback) or as a very nonlinear device – a comparator. Let’s see how! “Differential” V0 depends only on difference (V+  V-) The output cannot be larger than the supply voltages. It will limit or “clip” if we attempt to go too far. We call the limits of the output the “rails”. EE 42 fall 2004 lecture 41

  13. Circuit model gives the essential linear part • But V0 cannot rise above some physical voltage related to the positive power supply VCC (“ upper rail”) V0 < V+RAIL • And V0 cannot go below most negative power supply, VEE i.e., limited by lower “rail” V0 > V-RAIL (a) V-V near origin (b) V-V over wider range upper “rail” V0 (V) V0 (V) 3 0.2 2 + + VIN 0.1 1 V0   VIN(V) VIN(V) 1 3 3 2 1 2 10 30 30 20 10 20 1 lower “rail” 2 .2 3 WHAT ARE I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN DIFFERENTIAL AMPLIFIER ? Example: Amplifier with gain of 105, with max V0 of 3V and min V0 of 3V. EE 42 fall 2004 lecture 41

  14. - - A A ( ( V V V V ) ) Differential Amplifier + + - - VDD=2V V0= V0= V+ + V+ + A A  V  V VSS=0 THE RAILS The output voltage of an amplifier is of course limited by whatever voltages are supplied (the “power supplies”). Sometimes we show them explicitly on the amplifier diagram, but often they are left off. Ifthe supplies are 2V and 0V, the output cannot swing beyond these values. (You should try this experiment in the lab.) For simplicity we will use the supply voltages as the rails. So in this case we have upper rail = 2V, lower rail = 0V. EE 42 fall 2004 lecture 41

  15. (c) Same V0 vs VIN over even wider range V0 (V) 3 2 (b) V-V over wide range 1 upper “rail” 1 V0 (V) 2 VIN(V) 3 3 2 1 VIN(V) 1 3 3 2 1 2 10 30 30 20 10 20 lower “rail” 1 2 3 I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN DIFFERENTIAL AMPLIFIER (cont.) Example: Amplifier with gain of 105, with upper rail of 3V and lower rail of 3V. We plot the V0 vs VIN characteristics on two different scales EE 42 fall 2004 lecture 41

  16. AND A C=A·B B A A NOR C=A+B OR B B A B EXCLUSIVE OR A NOT Logic Gates These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND, NOR, and EXCLUSIVE OR. A NAND C = B C = EE 42 fall 2004 lecture 41

  17. Evaluation of Logical Expressions with “Truth Tables” The Truth Table completely describes a logic expression In fact, we will use the Truth Table as the fundamental meaning of a logic expression. Two logic expressions are equal if their truth tables are the same EE 42 fall 2004 lecture 41

  18. Some Useful Theorems • 1) • 2) • 3) • 4) • 6) • 7) • 8) • 9) Defined from form of truth tables Communicative Associative Each of these can be proved by writing out truth tables Distributive } de Morgan’s Laws EE 42 fall 2004 lecture 41

  19. Clearly this expression is realized with three NAND gates: one three-input NAND for , one for , and one two-input gate to combine them: A B C Y D E F Synthesis Designing the combinatorial logic circuit, con’t Method 3: NAND GATE SYNTHESIS. If we may use De Morgan’s theorem we may turn the sum-of-products expression into a form directly implementable entirely with NAND gates. (We also need the NOT function, but that is accomplished by a one-input NAND gate). function. Starting with any SUM-OF-PRODUCTS expression: Y = ABC+DEF we can rewrite it by “inverting” with De Morgan: The NAND realization, while based on DeMorgan’s theorem, is in fact much simpler: just look at the sum of products expression and use one NAND for each term and one to combine the terms. EE 42 fall 2004 lecture 41

  20. (X-OR function) C B A Y A X (No connection) B Synthesis Designing the combinatorial logic circuit, con’t Method 3: NAND GATE SYNTHESIS (CONTINUED). Two Examples of SUM-OF-PRODUCTS expressions: We could make the drawings simpler by just using a circle for the NOT function rather than showing a one-input NAND gate EE 42 fall 2004 lecture 41

  21. VDD = 3V - SP is closed if VIN < VDD by 2V SP + RP VOUT VIN + + RN Input Output SN is closed if VIN > VSS by 2V + SN - - - VSS = 0V Controlled Switch Model of Inverter Note top, type P, switch is “upside down” The idea: If input is 3V then top switch open, bottom one closed. And if input is 0V, bottom switch is open, and top switch closed. Thus we connect the output (through one of the resistors RP or RN) to either ground or VDD. EE 42 fall 2004 lecture 41

  22. p p CMOS • Both NMOS and PMOS on a single silicon chip • NMOS needs a p-type substrate • PMOS needs an n-type substrate • But we can build in the same substrate by changing doping type D G G D S S oxide n-well n n p-well We can butt the p and n together, or even let, for example the entire non n-well region be p type. EE 42 fall 2004 lecture 41

  23. VDD CMOS Inverter p-ch IN Inverter OUT VDD n-ch OUT IN Example layout of CMOS Inverter Basic CMOS Inverter EE 42 fall 2004 lecture 41

  24. Al “wires” VDD IN PMOS Gate N-WELL OUT NMOS Gate GROUND EE 42 fall 2004 lecture 41

  25. metal metal + + - - NMOS Transistor VDS drain VGS gate ID IG source metal oxide insulator n-type n-type p-type metal + VGS _ G IG ID S D - VDS + EE 42 fall 2004 lecture 41

  26. NMOS I-V Characteristic G + VGS _ IG • Since the transistor is a 3-terminal device, there is no single I-V characteristic. • Note that because of the insulator, IG = 0 A. • We typically define the MOS I-V characteristic as ID vs. VDS for a fixed VGS. • The I-V characteristic changes as VGS changes. ID S D - VDS + EE 42 fall 2004 lecture 41

  27. NMOS I-V Curves ID triode mode saturation mode VGS = 3 V VDS = VGS - VTH(n) VGS = 2 V VGS = 1 V VDS cutoff mode (when VGS < VTH(N)) EE 42 fall 2004 lecture 41

  28. Saturation in a MOS transistor • At low Source to drain voltages, a MOS transistor looks like a resistor which is “turned on” by the gate voltage • If a more voltage is applied to the drain to pull more current through, the amount of current which flows stops increasing→ an effect called pinch-off. • Think of water being sucked through a flexible wall tube. Dropping the pressure at the end in order to try to get more water to come through just collapses the tube. • The current flow then just depends on the flow at the input: VGS • This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source. EE 42 fall 2004 lecture 41

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