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טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. PowerPC based reliable computer. Characterization presentation. Students: Guy Derry Gil Wiechman Instructor: Isaschar Walter Winter 2003. Problem:
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טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל PowerPC based reliable computer Characterization presentation Students: Guy Derry Gil Wiechman Instructor: Isaschar Walter Winter 2003
Problem: In space, VLSI devices are exposed to large amounts of cosmic radiation, since there is no atmosphere to filter it out. Therefore, the MTBF of electronic equipment in space is greatly reduced. Solution: Design of redundant devices to be used in space systems, hence increasing overall system reliability.
Project goals • Develop a working prototype of a satellite computer, implementing the peripheral device monitoring and operation algorithm. • Examine policies of managing redundant peripherals and select one. • Implement the chosen algorithm on the Virtex II Pro FPGA board
Project Assumptions In this project, we assume correct operation of the software, on a correctly operating single processor. The issue of multiple processors handling is examined under a different project, running concurrently to ours.
General block diagram Off-Board Peripherals interface On-Board Peripherals Xilinx Virtex-II Pro FPGA
P1 P2 P3 P1 P2 P3 Monitor Monitor Memory-fault Monitor Memory-fault Monitor M1 M2 M3 M1 M2 M3 General block diagram Monitor LUT 101001001010010010100 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 101001001010010010100 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 010010010100100101010 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 PPC405
S/W & H/W Requirements • Xilinx Virtex-II Pro mounted on evaluation board incl. Serial / USB / Other ports • Software running on RT OS (Wind River) which communicates with connected peripherals and implements a monitoring & fault tolerant operation algorithm
Project schedule – Qtr. I • Wk. I: Study the PPC405 Processor core • Wk. II: Study the Virtex-II Pro component design • Wk. III: Get familiar with VHDL development environment • Wk. IV: Write a “Hello, world!” program for the Virtex-II Pro
Project schedule – Qtr. I(cont.) • Wk. V: Expand programming abilities; study & work with peripheral interface • Wk. VI: Continue working on FPGA / Study the monitoring algorithm1 • Wk. VII: Continue working on FPGA / Begin implementing the monitoring algorithm 1 Depending on component availability
Project schedule - First Semester Goals • Full operation of all units (on & off board), incl. unit disconnection ability • Multiple peripheral unit operation ability • Fault tolerant memory access
Project schedule - Second Semester Goals • Most of the work on redundancy will be performed during the second semester • Final goal: fully operative system incl. a simulation of an identification and correct operation in case of a faulty device
