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A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8)

A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8). Speaker: Bing-Yu Hsieh MediaTek Inc., Hsin-Chu, Taiwan Authors:

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A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8)

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  1. A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8) Speaker: Bing-Yu Hsieh MediaTek Inc., Hsin-Chu, Taiwan Authors: Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho

  2. Outline • Overview • System Architecture • Solutions for Low Power Issue • Performance Comparison • Summary

  3. Overview • Highly Integrated Commercial Application • Integrated Analog Front-End • Built-in 1.5Gb/s SATA PHY • On-Chip Write Strategy Generator • PRML Read Channel • Low Power Control • Supports Multiple Format of Discs • CD/DVD-dual/DVD-RAM Record/Playback Operation Speed up to 56xS/18xS/16xS

  4. System Architecture of FMSOC Spindle Pick-up

  5. Solutions for Low Power Issue Optimization Efficiency • Efficient DRAM Access • Adaptive Clock Control • Multiple Clock Design • Clock Suppression and Gating • Voltage Partition • Reduce Clock Buffer ARCHITECTURE RTL BACK-END

  6. Efficient DRAM Access - Bandwidth • Large DRAM B.W. Requirement • DRAM is shared to multiple functions • DRAM Access Efficiency • Performance Index: Ave. cycle # to access each word • Dominated by the times of DRAM Row Addr. Change

  7. Efficient DRAM Access - Recursive Encode

  8. Adaptive Clock Control - Background • Data Rate of Optical Storage Varies with: • Rotation Speed • Radius of the Access Point • Numerical Controlled Oscillator • Adaptive Control with Linear Steps

  9. Adaptive Clock Control - Architecture Automatically adjust system clock with linear increments according to a throughput rate indicator

  10. Adaptive Clock Control - Performance . q Fixed Freq. 73MHz e 67MHz r 70 (94.4mA) F ) z k (90.1mA) H 60 56MHz c o M l Adaptive (81.5mA) 50 : C (Digital Core Current) t 42MHz i Freq. n m 40 u (70.4mA) e ( t s 30 y S 9.2 12.5 15.3 16 DVD Read Speed (unit: xS)

  11. Chip Micrograph

  12. Chip Specification

  13. Comparisons of the Chip Performance

  14. Summary • Performance • Single Chip SoC with CD/DVD-dual/RAM Operation Speed up to 56xS/18xS/16xS • Integration • SATA, WSG, PRML, Analog Front-End Integration • 0.18 m CMOS with 27.5 mm2die size • 772mW @ 16xS DVD playback • Architectural Optimization for Low Power • Recursive Parity Encode • Adaptive Clock Control

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