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Field Trip to Harris Semiconductor

Field Trip to Harris Semiconductor. Monday (February 28th) Leave at 9:00 AM from Stocker There will be a class on the 25th!! Will discuss Quiz 3 Tour from ~1:30 PM to 4 PM Arrive in Athens after 8PM Bring cash for food No MAKE-UP please. COMBINATIONAL LOGIC. Read 4.1, 4.2

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Field Trip to Harris Semiconductor

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  1. Field Trip to Harris Semiconductor • Monday (February 28th) • Leave at 9:00 AM from Stocker • There will be a class on the 25th!! • Will discuss Quiz 3 • Tour from ~1:30 PM to 4 PM • Arrive in Athens after 8PM • Bring cash for food • No MAKE-UP please

  2. COMBINATIONAL LOGIC Read 4.1, 4.2 Start Reading 4.3 (dynamic CMOS)

  3. Out MN In C N L M 1 > M 2 > M 3 > MN C 3 In M 3 3 Distributed RC-line C M 2 In 2 2 C In M 1 1 1 Fast Complex Gate - Design Techniques • Progressive Sizing: As long as Fan-out Capacitance dominates Example 4.3: no sizing: tpHL = 1.1 nsec with sizing: tpHL = 0.81 nsec Can Reduce Delay by more than 30%!

  4. critical path critical path C C L In L M 3 In M 1 3 1 C C 2 In M 2 M 2 2 In 2 2 C C In M 1 1 In M 3 3 1 3 (a) (b) Fast Complex Gate - Design Techniques • Transistor Ordering

  5. Fast Complex Gate - Design Techniques • Improved Logic Design

  6. Fast Complex Gate - Design Techniques • Buffering: • Isolate Fan-in from Fan-out C C L L Read Example 4.5

  7. V DD • N transistors + Load Resistive • V = V OH DD Load R L R • V = DN OL VDD R + R F DN L In 1 • Asymmetrical response In PDN 2 In • Static power consumption 3 = 0.69 R C • t pLH L L V SS Ratioed Logic

  8. Ratio Based Logic • Problems with Resistive Load • IL = (VDD – Vout) / RL • Charging current drops rapidly once Vout starts to rise • Solution: Use a current source! • Available current is independent of voltage • Reduces tpLH by 25%

  9. Load Lines of Ratioed Gates

  10. V V DD DD Depletion PMOS V < 0 Load Load T V SS F F In In 1 1 In In PDN PDN 2 2 In In 3 3 V V SS SS depletion load NMOS pseudo-NMOS Active Loads

  11. Active Loads • Depletion mode NMOS load • VGS = 0 • IL ~ (kn, load / 2) (|VTn|)2 • Deviates from ideal current source • Channel length modulation • Body effect • VSB != VDD • varies with Vout • reduces |VTn|, hence IL for increasing Vout

  12. Active Loads • Pseudo-NMOS load • No body effect, VSB = 0V • VGS = - VDD , higher load current • IL = (kp / 2) (VDD - |VTn|)2 • Larger VGS causes pseudo-NMOS load to leave saturation mode sooner than NMOS

  13. Pseudo-NMOS For Vin = VDD: NMOS linear PMOS saturated Read PP 206, 207, Example 4.6

  14. Pseudo-NMOS NAND Gate VDD Out GND

  15. Improved Loads Standby mode reduces power dissipation

  16. V V DD DD M1 M2 Out Out A A PDN1 PDN2 B B V V SS SS Improved Loads (2) Dual Cascode Voltage Switch Logic (DCVSL)

  17. Out Out B B B B A A XOR-NXOR gate Example

  18. B Out A Switch s t Out u p n Network B I B Pass-Transistor Logic • N transistors • No static consumption

  19. C = 5 V C = 5 V M 2 A = 5 V B A = 5 V M n B M C 1 L does not pull up to 5V, but 5V - V B Threshold voltage loss causes static power consumption NMOS-only switch V TN

  20. C C A A B B C C Solution 1: Transmission Gate

  21. Resistance of Transmission Gate

  22. S S Pass-Transistor Based Multiplexer S VDD GND In1 In2 S

  23. B B M2 A A F M1 M3/M4 B B Transmission Gate XOR

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