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Enhancing Bounded Sequential Equivalence Checking with Range-Equivalent Circuit Minimization

This work focuses on improving bounded sequential equivalence checking (BSEC) through the integration of range-equivalent circuit minimization. We explore significant concepts like miter construction and the use of SAT solvers for verifying equivalence within a limited timeframe. Our experimental results demonstrate enhanced performance in circuit verification times and accuracy by utilizing optimized techniques for circuit minimization. Future work aims to address existing bugs, expand case studies, and refine methods for fixed-point state checking in sequential circuits.

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Enhancing Bounded Sequential Equivalence Checking with Range-Equivalent Circuit Minimization

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  1. Enhancing Bounded Sequential Equivalence Checkingwith Range-Equivalent Circuit Minimization Speaker: Chih-Chung Wang Adviser: Chun-Yao Wang Yung-Chih Chen Date: 2012. 1. 28

  2. Outline • Introduction • BSEC • RECM • NAR • Enhancing BSEC with RECM • Experimental Result • Future Work

  3. Introduction • Sequential Equivalence Checking • Equivalence Checking • Miter • Output 0 if the same • SAT Solver • UNSAT if the same F O G

  4. Introduction • Sequential Equivalence Checking • Sequential Circuit • Combinational Circuit • Primary Input / Output (PI / PO) • Latch • Pseudo Primary Input / Output (PPI / PPO) State Transition Graph (STG) PI PO Combinational Circuit S0 S1 States of Combinational Logic Circuit Part S3 PPO PPI S2 Latch S4 Sn … …

  5. Introduction • Sequential Equivalence Checking • Bounded Sequential Circuit • Limited number of states • Equivalence verifiable by setting bound k • ex. set k = 2 State Transition Graph (STG) PI PO Combinational Circuit S0 S1 States of Combinational Logic Circuit Part S3 PPO PPI S2 Latch S4 Sn … …

  6. Introduction • Sequential Equivalence Checking PI PO Combinational Circuit PPO PPI Latch

  7. Introduction • Range-equivalent circuit • Range • Range Equivalent • Range-equivalent circuit minimization

  8. Bounded Sequential Equivalence Checking (BSEC) • Bounded: timeframe k • Typical BSEC • Miter construction • SAT solver • Unroll • Sequential → Combinational …

  9. Introduction • Circuit optimization • Node merging • Node addition and removal (NAR)

  10. Enhancing BSEC • Using range-equivalent circuit minimization while building BSEC model • Range – every set of output • Equivalence checking – checking all possible input

  11. Enhancing BSEC • Range-equivalent circuit creation • Taking too much time to run • Might have runtime error • Using a smaller timeframe to create range-equivalent circuit • Replacing the circuit 0 to n • Connecting to the next timeframe n+1 • Repeatedly running until n equals k

  12. Enhancing BSEC n • Using a smaller timeframe n to create range-equivalent circuit • Replacing the circuit 0 to n • Connecting to the next timeframe n+1 • Repeatedly running until n equals k

  13. Enhancing BSEC n+1 • Using a smaller timeframe n to create range-equivalent circuit • Replacing the circuit 0 to n • Connecting to the next timeframe n+1 • Repeatedly running until n equals k

  14. Enhancing BSEC • Using a smaller timeframe n to create range-equivalent circuit • Replacing the circuit 0 to n • Connecting to the next timeframe n+1 • Repeatedly running until n equals k

  15. Resyn2 Original Optimized Construct miter pMiter Resyn2 NAR Optimize pMiterOpt timeframe: 0 Resyn2 Add one timeframe pFrames Range-equivalent circuit replacement pFrames timeframe: n no n = k ? yes pFrames Resyn2 Optimize NAR pFramesOpt timeframe: k Resyn2 SAT solver

  16. Enhancing BSEC • Loop from timeframe 0 to k • One timeframe addition • Range-equivalent circuit minimization • Equivalence checking • Preprocessing of range • Adding POs at all PPIs (pseudo primary inputs) • Removing no fanout nodes • Removing verified POs

  17. Flow pMiter timeframe: 0 One timeframe addition Adding POs at all PPIs Removing all old POs and no fanout nodes timeframe: n Range-equivalent circuit replacement SAT solver verification no n = k ? yes timeframe: k pFrames

  18. Experimental Result • ic5-8, ic14-19 • GNU/Linux • 8 core, 3.0GHz • x86_64 • Compare • Original: Typical BSEC • resyn2 • NAR + resyn2

  19. Resyn2 Original Optimized Construct miter pMiter Resyn2 Optimize NAR pMiterOpt timeframe: 1 Resyn2 Unroll k times pFrame Resyn2 Optimize NAR pFrameOpt timeframe: k Resyn2 SAT solver

  20. Resyn2 Original Optimized Construct miter pMiter Resyn2 NAR Optimize pMiterOpt timeframe: 0 Resyn2 Add one timeframe pFrames Range-equivalent circuit replacement pFrames timeframe: n no n = k ? yes pFrames Optimize NAR Resyn2 pFramesOpt timeframe: k Resyn2 SAT solver

  21. Experimental Result • Experiment 1 • Setting timeframe k • Comparing time spent (second) • Range-equivalent circuit creation • SAT solver • Total • Time limit • 36000 seconds

  22. Experimental Result

  23. Experimental Result • Experiment 2 • Time limit • 1000 seconds • Comparing how many timeframes can be checked (k) • Recording the total time until the last timeframe

  24. Experimental Result

  25. Experimental Result • Some cases can run very fast while building BSEC model • Ex. b04, usb_phy • : Node number in timeframe i Range-equivalent circuit minimization Timeframe addition

  26. Future Work • Fixing the bugs • systemcdes, i2c, des_area • Fixed-point

  27. Fixed-point • : the set of all reachable states at the i-th iteration • The sets of the reachable states in two consecutive iterations are identical • i.e., = initial state fixed-point … reachable states

  28. End

  29. Experimental Result

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