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Introduction to SystemC

Introduction to SystemC. Background. From ASIC to System on a Chip. Multimedia Game System. Wireless GSM Pocket Communicator. Satellite (DVB) Video Broadcasting. The Design Challenge. Design Methodology and EDA Enable SoC. Source: OSCI. Synopsys RTL to GDS II Flow.

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Introduction to SystemC

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  1. Introduction to SystemC

  2. Background

  3. From ASIC to System on a Chip Multimedia Game System Wireless GSM Pocket Communicator Satellite (DVB) Video Broadcasting The Design Challenge Design Methodology and EDA Enable SoC Source: OSCI

  4. SynopsysRTL to GDS IIFlow C Compilerassembler link editor (IDE) System Level Design in Perspective HWImplementation Verification &Analysis SWImplementation SystemLevel IP System Level Design System Soft IP RTL Hard IP Physical Source: OSCI

  5. Functional System Specification (HW, SW, environment) in C/C++ HeterogeneousMultilevel Verification analogmixed signalHW BlockDesign digitalHW BlockDesign SW Block Design System Architecture System Level HW/SW CoDesignBlock Creation and System Integration Source: OSCI

  6. Key Challenge: Heterogeneity • Abstractions • multiple domain specific abstractions • various levels of detail • Languages • multiple languages • dedicated tools • Teams • mixed/multiple teams • multiple disciplines & background • physically distributed

  7. HDL based flow Source: OSCI

  8. The Role of Executable Specifications Executable Specification • Systems Company • Functional system design • Validate architecture • Feedback system level IP models and requirements • Semiconductor Company • Define / Design architecture for vertical market • Modify architecture to meet requirements • Deliver updated executable specification to customer for validation Source: OSCI

  9. Algorithms Architecture Application • Proprietary Languages • Proprietary C Extensions • C++ Class Libraries • Using C/C++ • Using C/C++ Need a Common Language • Common C/C++ Style to Enable the Industry • - to model/exchange system level IP • - to build interoperable tools infrastructure Source: OSCI

  10. Open SystemC Initiative (1999.9; OSCI) www.SystemC.org Not for profit organization Members: Synopsys, CoWare, Frontier, Motorola, NEC, TI, C Level Design, Cadence and so on SpecC Technology Open Consortium (1999.11; STOC) www.SpecC.org Sponsored out of UC Irvine Members: NEC, Hitachi, Forte (CynApps), Cadence, Mentor C initiatives

  11. SystemC v.s. SpecC

  12. Overview

  13. SystemC heritage Synopsys ATG Synopsys Scenic SystemC V0.90 (’99) UC Irvine (’96) Synopsys Fridge Frontier A|RT (’91) SystemC V1.0 (’00) Imec (’92) CoWare N2C (’97) SystemC V1.1 (’00) SystemC V2.0 (’01)

  14. Historical evolution • Sept. 1999: SystemC launched with OSCI (Open SystemC Initiative: www.SystemC.org) • Sept. 1999: SystemC V0.9 • Feb. 2000: SystemC V0.91 • March 2000: SystemC V1.0 (fixed-point package added) • June 2000: SystemC V1.1B • 2000: SystemC V1.2B • Oct. 2001: SystemC V2.0 • 2002: SystemC V2.0.1

  15. What is SystemC • SystemC is modeling platform consisting of a set of C++ class library, plus a simulation kernelthat supports hardware modeling concepts at the system level, behavioral level and register transfer level. • SystemC enables us to effectively create a cycle-accurate model of software algorithm, hardware architecture, and interfaces of System-on-a-Chip. • Program in SystemC can be an executable specification of the system.

  16. The C++ Class Library Approach • Create C++ class libraries to provide missing modeling elements • Do not extend C/C++ by proprietary language constructs • Support usage of ANSI-compliant C++ compiler

  17. Can C/C++ be used as is? • C/C++ does not support • Concurrency • hardware and systems are inherently concurrent, i.e. they operate in parallel • Reactivity • hardware is inherently reactive, i.e. it responds to a stimuli and is in constant interaction with its environment, which requires handling of exceptions

  18. Can C/C++ be used as is? (cntd.) • C/C++ does not support • Hardware data types • bit type, bit-vector type, multi-valued logic type, integer types and fixed-point types of arbitrary size/precision • Hardware style communication • signals, protocols, etc. • Notion of time • time sequenced operations

  19. … And What SystemC is Not • A replacement for Verilog and VHDL and associated simulation tools • A replacement for domain specific tools like COSSAP • The most efficient simulation and debugging environment for C++-based designs • A compiled simulator with its own debugger would be a better environment

  20. What SystemC Is Useful For ... • Modeling system architecture • Untimed • Transaction-accurate • Clock-cycle-accurate • Modeling hardware(processors, peripherals, ASSPs, ASICs) • Algorithmic • Behavioral • RTL • Modeling software

  21. Processes for concurrency Clocks  for time Hardware data types  bit vectors, 4-valued logic, fixed-point types, arbitrary precision integers Waiting and watching for reactivity Modules, ports, and signals for hierarchy Channel, interface, andevent abstract communications SystemC features

  22. SystemC V2.0 language structure

  23. SystemC design environment

  24. Matlab Esterel SpecC SDL Others UTF Design Exploration Performance Analysis HW/SW partitioning Functional decomposition SystemC Untimed Functional Assign ‘execution time’ Timed Functional TF HW / SW Partition Architectural mapping Refine communication Bus Cycle Accurate Abstr. RTOS Task Partitioning BCA Refine behavior Target RTOS/Core Cycle Accurate RTL RTOS Hardware Software Abstractions

  25. Key to the methodology is that a design may be refined in a gradual step-wise fashion, rather than in one giant step… it need not be “all or nothing”. UTF UTF UTF UTF UTF TF UTF UTF UTF TF TF BCA RTL UTF RTL Gradual Refinement of the Design Simulation Details added to portions of the system. Simulation Simulation

  26. Synthesis Subset of C++ ANSI C++ All Object Oriented Features Inheritance Templates RTTI SystemC ANSI C Pointers Recursion Goto malloc free Dereference (*) Address-of(&) Member Selector (->) Volatile types .asm SYNTHESIZABLE C++ SUBSET (Current Level)

  27. SystemC home page

  28. Basic Concepts

  29. Example - Adder with Register Adder Register a temp c b clock

  30. #include “systemc.h” struct adder_reg : sc_module { sc_in< sc_int<8> > a; // input port sc_in< sc_int<8> > b; // input port sc_out< sc_int<9> > c; // output port sc_in<bool> clock; // clock // Internal signal sc_signal< sc_int<9> > temp; // Adder process void add() { temp = a + b; } // Register update process void reg() { c = temp; } // Constructor SC_CTOR(adder_reg) { SC_METHOD(add); sensitive << a << b; SC_METHOD(reg); sensitive_pos << clock; } }; Example - Adder with Register

  31. SystemC structure User Module User Module User Module C++ Class Lib. Simulation Kernel (Event Scheduler) Multi-Threading (QT: Quick Thread) Operating System

  32. System Process Process Module Module Module Process Process Process Process Process Process Process SystemC system • A system consists of a set of concurrent processes that describe functionality. • Processes communicate with each other through channels. • Processes can be combined into modules to create hierarchy.

  33. SystemC module • Module: basic building block to partition a design • a hierarchical entity in which processes and other modules are instantiated • SC_MODULE(module_name) {elements_of_module} • Can contain the following elements • Ports • Constructors • Data members – local data, local signals • Function members – processes • Other modules #define SC_MODULE( module_name ) struct module_name : sc_module

  34. SystemC port • Ports: the external interface passing information to and from a module • modes in in, out and inout • sc_in<data_type>port_name: transfers data into a module. • sc_out<data_type>port_name: transfers data out from a module. • sc_inout<data_type>port_name: transfers data both into and out of a module depending on module operation. • Clock related: • sc_in_clk name (sc_in<bool> name) • sc_out_clk name (sc_out<bool> name) • sc_inout_clk name (sc_inout<bool> name) • for backward compatibility reasons

  35. SystemC port • Ports: the external interface passing information to and from a module • Resolved ports: • sc_in_rv<width> name • sc_out_rv<width> name • sc_inout_rv<width> name Remarks: Multiple drivers can be attached at resolved signal, while only one driver can be attached at unresolved signal.

  36. SystemC signal • Signal: create connections between module ports allowing modules to communicate • A signal connects the port of one module to the port of another module. • represent the physical wire • Member functions: read(); write(); event(); posedge(); negedge(); delayed()

  37. SystemC signal • Signal: create connections between module ports allowing modules to communicate • unresolved signal - only one driver can be attached • sc_signal<data_type> name • resolved signal - multiple drivers can be attached • sc_signal_rv<width> name: it is a resolved vector of sc_logic signals.

  38. Port and signal MM MA MB sc_signal<int> sc_signal_rv<4> sc_inout_rv<4> A sc_in_rv<4> C MC sc_out_rv<4> B 0: false 1: true X: unknown Z: hi-impedance or floating

  39. Example A=0 A=0 B=Z D B=X D C=Z C=Z A=1 A=1 B=Z D B=X D C=Z C=Z

  40. SystemC process • Process: the basic unit of execution • SystemC has the concept of Processes (Methods, Threads, and Clocked Threads) to model the parallel activities of a system. • Processes within a module are concurrent, and they execute whenever one of their sensitive inputs changes. • Processes are not hierarchical, so no process will call another process directly, i.e., process cannot have a process inside another process.

  41. SystemC process • Process: the basic unit of execution • Three types: type determines how the process is called and executed • Method process (SC_METHOD()) – cannot contain wait(); better speedup; not thread of execution • Thread process (SC_THREAD()) - can contain wait() • Clocked thread process (SC_CTHREAD()) - only triggered on one edge of one clock - good to synthesis

  42. Conceptual thread of execution sc_main() Module instantiation and port connection sc_start(….) Zero simulation time Process(es) of module(s) simulation return(0)

  43. sc_clock clock(“clock”, 20, 0.5, 2, false); clock 2 12 22 32 SystemC clock • Clock is a special object generating timing signals used to synchronize events in simulation. • sc_clock clock_name (name, period, time_unit, duty_cycle, time_to_first_edge, time_unit, first_edge_positive); • Duty cycle: the ratio of the high time to the entire clock period.

  44. SystemC data types • SystemC supports C++ built in data types • bool; char; short; int; long; float; double; • unsigned char; unsigned short; unsigned int; unsigned long; • SystemC data types • Boolean types • sc_bit - 2 value single bit: ‘0’ (false), ‘1’ (true) • Logic types • sc_logic - 4 value single bit: ‘0’, ‘1’, ‘X’, ‘Z’ • Integer types (fixed precision) • sc_int<n>, sc_uint<n> - 1 to 64 bit signed & unsigned integer • sc_bigint<n>, sc_biguint<n> - more than 64 bit signed & unsigned integer

  45. SystemC data types • SystemC data types • Boolean/Logic vector types (arbitrary precision) • sc_bv<n> - arbitrary sized 2 value Boolean vector type • sc_lv<n> - arbitrary sized 4 value logic vector type • Fixed point types • sc_fixed<>, sc_ufixed<>: static/templated • sc_fix, sc_ufix: nonstatic

  46. Integer, floating-point, fixed-point Decimal (binary) point Integer Fixed-point Floating-point x2

  47. Impact on simulation speed Faster Native (built-in) C++ data type Fixed precision integer data type Arbitrary precision integer data type sc_biguint<n> Slower sc_bv<n> sc_lv<n>

  48. SystemC data types More detailed faster

  49. SystemC operators • Bitwise: ~(not); &(and); |(or); ^(xor); >>(shift right); <<(shift left) • Arithmetic: +; -; *; /; %; <<; >> • Assignment: =; +=; -=; /=; %=; &=; |=; ^=; <<=; >>= • Equality: ==; != • Relational: <; <=; >; >= • Auto-inc/dec: ++; -- • Bit select: [n] • Part select: range() • Concatenation: (,) • Reduction: and_reduction(); or_reduction(); xor_reduction() Note: Arithmetic shift preserves the sign bit.

  50. SystemC tracing • SystemC provides functions to create waveform in the following formats • VCD - value change dump • sc_create_vcd_trace_file(“file_name”)  file_name.vcd • WIF - ASCII waveform intermediate format • sc_create_wif_trace_file(“…”)  file_name.awif • ISDB - integrated signal data base • sc_create_isdb_trace_file(“…”)  file_name.isdb

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