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203MHz OR1200 Design with CTS, Power Grid, and DFM Features Integration Presentation

203MHz OR1200 Design with CTS, Power Grid, and DFM Features Integration Presentation Matt Slowik, slowik.matthew@gmail.com VLSI2 12.2.2011 Final Project Directory: /home/projects/courses/fall_11/ee382m-17145/project_fall_11/results/final/ Additional Details:

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203MHz OR1200 Design with CTS, Power Grid, and DFM Features Integration Presentation

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  1. 203MHz OR1200 Design with CTS, Power Grid, and DFM Features Integration Presentation Matt Slowik, slowik.matthew@gmail.com VLSI2 12.2.2011 Final Project Directory: • /home/projects/courses/fall_11/ee382m-17145/project_fall_11/results/final/ • Additional Details: • /home/projects/courses/fall_11/ee382m-17145/project_fall_11/results/final/README

  2. icc.flow.tcl – Top level OR1200 APR Script <- SETUP LIBS <- TECHNOLOGY DESCRIPTION <- SETUP CLOCKS <- REMOVE EMPTY PORTS

  3. icc.flow.tcl – Top level OR1200 APR Script... continued <- UPDATE_PG Extract_rc -coupling_cap

  4. icc.floorplan.tcl – Top level OR1200 Floorplan Script

  5. icc.floorplan.tcl – Top level OR1200 Floorplan Script… continued

  6. OR1200 Floorplan Organization Notice: Logical cell boundaries, Fixed arrays, array placement blockages, pin placements Array orientations, cell group placement drift

  7. OR1200 Floorplan Organization.. Continued • # flattening some hierarchies -- this is needed to converge stall paths • current_design "or1200_mult_mac" • ungroup -flatten -all • current_design "or1200_lsu" • ungroup -flatten -all • current_design "or1200_ic_top" • ungroup -flatten -all • current_design "or1200_dc_top" • ungroup -flatten -all • current_design "or1200_dmmu_top" • ungroup -flatten -all • current_design "or1200_immu_top" • ungroup -flatten -all • current_design "or1200_top" • ungroup [get_cells -hierarchical or1200_genpc] • ungroup [get_cells -hierarchical or1200_freeze] • ungroup [get_cells -hierarchical or1200_sprs] • ungroup [get_cells -hierarchical or1200_except] • ungroup [get_cells -hierarchical or1200_ctrl] • ungroup [get_cells -hierarchical or1200_if] • ungroup [get_cells -hierarchical or1200_lsu] • Notice the slim vertical placement blockages…

  8. OR1200 Power Grid Idea #1 Idea #2 Idea#2 has twice the number of vias for each VDD and VSS supply, while using half the vertical routing tracks. Used idea#2 to keep be able to route the design cleanly at 3.1mm^2 and to satisfy current density constraints. Icc.powergird.tcl file script used to implement Idea#2

  9. icc.powergrid.tcl – Power Grid Script <- Sparse, but satisfies constraints from Mostafa’s via current densities

  10. <- CREATE_RAILS_IN_BBOX

  11. Power Grid Visual

  12. OR1200 Clock Tree Synthesis

  13. OR1200 Area Audit • icc_shell> set OR1200_width [get_bbox_xh [get_attribute -class die_area [get_die_area] bbox]] • 2164.140 • icc_shell> set OR1200_height [get_bbox_yh [get_attribute -class die_area [get_die_area] bbox]] • 1441.440 • icc_shell> set AREA [expr $OR1200_width * $OR1200_height] • 3119477.9616 • This corresponds to 3.119mm^2 << 4mm^2 goal

  14. OR1200 LVS/DRC Audit Ran verify_lvs with the “ignore_floating_port” switch This is because sequential cells in the library output Q and QN even though the design does not require it (thus leaving them floating in the layout)

  15. OR1200 Wrap Up Feedback: Tools – Significant ramp up required on Synopsys Design Compiler, ICC, Primetime. More documentation needed if possible Different standard cell library - Sequentials both have Q and Qbar outputs that aren’t always utilized (wasted power, floating pins at full chip) More detail to array creation – Arrays did not pitch match to standard cell library (Made for interesting partial filler cell insertion) Also since they took up a majority of the area I should have investigated into different aspect ratio choices Power Grid Creation – Turned out to be a difficult task. I was not able to get built in procedures to work correctly.

  16. BACKUP

  17. Technology Description - TSMC Standard Cell Library 180nm Process Technology Standard Cell Height = 5.04um Minimum Cell Width = 0.66um Layer direction/pitch/spacings in microns: BACK

  18. BACK BACK <- CREATE_RAIL_STUBS

  19. <- COMPUTE_BBOX_BOOLEAN_NOT <- GET_OPEN_BBOXES BACK

  20. BACK

  21. BACK

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