1 / 13

ASPI9-2: DSP Multiprocessor Architectures mm5

ASPI9-2: DSP Multiprocessor Architectures mm5. Platform Comparison Agenda: Experiments with TI 320C55 C55 Architecture & DataPath C55 Complier & loop optimizations GSM EFR study Benchmarking C55 vs. ARM9-S (Hypo)Thesis/Method Experiments Results/Conclusion Summary.

georgier
Télécharger la présentation

ASPI9-2: DSP Multiprocessor Architectures mm5

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ASPI9-2: DSP Multiprocessor Architectures mm5 Platform Comparison Agenda: • Experiments with TI 320C55 • C55 Architecture & DataPath • C55 Complier & loop optimizations • GSM EFR study • Benchmarking C55 vs. ARM9-S • (Hypo)Thesis/Method • Experiments • Results/Conclusion • Summary Platform Comparison

  2. ASPI9-2: DSP Multiprocessor Architectures mm5 Platform Comparison Literature: • *MICRO35-paper* • *MICRO35 presentation* • TI TMS320C55x Platform Analysis (CISC architecture background) • ARM9-S Platform Analysis (RISC architecture background) • NORSIG paper Platform Comparison

  3. Data address generation (ALU) Shifter ALU 2 MAC Units Viterbi Program addresses Control sequence Instruction queue and decoder Source: TI TMS320C55x Architecture Overview Platform Comparison

  4. Experiments with TI 320C55 Goto Micro35 presentation Platform Comparison

  5. 16-bit data buses B Bus (Coefficient) C Bus D Bus x(n-m) h(m) x(n-m-1) Previous AC1 / AC0 * * MAC-2 MAC-1 + + AC0 AC1 Dual MAC Exploitation Platform Comparison

  6. GSM EFR Platform Comparison

  7. Benchmarking C55 vs. ARM9-S Goto Norsig Presentation Platform Comparison

  8. Summary • Compiler optimization is still insecure • Better compiler/architecture integration • Next step • application specific optimization • power optimization models Platform Comparison

  9. Summary Data and memory optimization techniques for embedded systems P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, P. G. Kjeldsberg April 2001  ACM Transactions on Design Automation of Electronic Systems (TODAES),  Volume 6 Issue 2 Full text available: pdf(339.91 KB) Additional Information: full citation, abstract, references, citings, index terms We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation. We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimizati ... Keywords: DRAM, SRAM, address generation, allocation, architecture exploration, code transformation, data cache, data optimization, high-level synthesis, memory architecture customization, memory power dissipation, register file, size estimation, survey Platform Comparison

  10. Summary Energy aware compilation for DSPs with SIMD instructions Markus Lorenz, Lars Wehmeyer, Thorsten Dräger June 2002  ACM SIGPLAN Notices , Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems,  Volume 37 Issue 7 Full text available: pdf(220.77 KB) Additional Information: full citation, abstract, references, citings, index terms The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. In this paper we present compiler optimizations with the aim of minimizing energy consumption of embedded applications: This comprises loop optimizations for exploitation of SIMD instructions and zero overhead hardware loops in order to increase performance and decrease the energy consumption. In addition, we use a phase coupled code generator ... Keywords: DSP, SIMD instruction, energy minimization, vectorization, zero overhead hardware loop Platform Comparison

  11. Experiments • Pure C code, no assembler optimizations. Platform Comparison

  12. ARM9E-S Architecture Overview Platform Comparison

  13. Compiler Features Comparison • Pragma: Extra information given to the compiler. • Intrinsic: Language extentions, usually translated as built-in functions by the compiler, that provide efficient access to some architectural features. Platform Comparison

More Related