R&D on monolithic and vertically integrated pixel sensors

1. R&D on monolithic and vertically integrated pixel sensors • Pixel detector R&D objectives: • High precision detectors in hostile environment • High intrinsic resolution • Low multiple scattering (low mass) • Close to the beam (background, radiation damage) • This turns into following technical requirements: • High granularity (resolution, occupancy) • High readout speed (complex processing) • Thin sensors (but keep high S/N) • Low power (0-mass cooling) • High fill factor (low mass) • Add functionalities (calibration, 0-suppression, clustering) • Radiation hardness • Of course: large signal, low noise, stable operation • And keep them affordable!

2. State of the art: hybrid pixles Face to face interconnection: ASIC - Sensor High granularity (resolution, occupancy) bump bonding limits pitch to O(50 µm) Pixel area 10000 µm² (Area for CMOS 0.25 µm) High readout speed (complex processing) Yes! Thin sensors (but keep high S/N) No (250 µm Sensor + ASIC + interconnect) Low power (0-mass cooling) No: liquid cooling needed High fill factor (low mass) No: 71% (ATLAS) Add functionalities (calibration, 0- suppression, clustering) ok, especially going to even smaller DSM Radiation hardness Yes (till 1015 n/cm²) Pitch: 50 mm

3. State of the art: CCDs • Standard Product • Used in SLD • R&D at RAL (ILC) High granularity (resolution, occupancy) Yes High readout speed (complex processing) No: frame readout O(10 µs) Thin sensors (but keep high S/N) Yes, but signal small anyway Low power (0-mass cooling) Yes (low temp. operation needed?) High fill factor (low mass) Tiling needed Add functionalities (calibration, 0-suppression, clustering) No (only in readout ASIC) Radiation hardness marginal (trapping) n T ~ n x m m Column parallel readout T ~ n

4. State of the art: DEPFETs FET on fully depleted silicon Baseline for Belle II PXD High granularity (resolution, occupancy) Yes High readout speed (complex processing) No: frame readout O(10 µs) Thin sensors (but keep high S/N) Yes, with good S/N Low power (0-mass cooling) Yes High fill factor (low mass) Yes: monolithic wafer scale sensors Add functionalities (calibration, 0-suppression, clustering) No (only in readout ASIC) Radiation hardness ok to 10 Mrad

5. CMOS Sensors Long History of CMOS Sensor R&D by Strasbourg group (IPHC, M. Winter): Mimosa series High granularity (resolution, occupancy) yes (depends on functionality/pixel) High readout speed (complex processing) marginal Thin sensors (but keep high S/N) yes (small signal anyway) Low power (0-mass cooling) yes (depends on speed and complexity) High fill factor (low mass) needs tiling Add functionalities (calibration, 0-suppression, clustering) difficult (only NMOS transistors) Radiation hardness marginal (cc by diffusion) EUDET Telescope: EU Funded (FP6): JRA1 of EUDET MAPS to be used in STAR upgrade Further R&D on CMOS Sensors: INFN (SLIM5,deep n-well) RAL Hawaii

6. Si pixel sensor BiCMOS analogue CMOS digital 3D Interconnection • Basic Problem: • How to integrate good sensors and good electronic circuits? • 3D Interconnection: • Two or more layers (=“tiers”) of thinned semiconductor devices interconnected to form a “monolithic” circuit. • Different layers can be made in different technology (high ohmic, BiCMOS, deep sub-m CMOS, SiGe,…..). • 3D is driven by industry: • Reduces R,L and C. • Improves speed. • Reduces interconnect power, x-talk. • Reduces chip size. • Each layer can be optimized individually.

7. Basics High density interconnect: SLID, DBI, ….. Pitches down to few µm Through silicon vias: electrical connection between two tiers and/or to outside deep anisotropic etching, aspect ratio 20:1 => < 50 µm wafer thickness

8. Intense R&D by industry Different technologies being pursued: eutectic bonding (SLID) direct bond interconnect (DBI) copper-copper bonding …… vias first <-> vias last (before or after CMOS process) etching, laser drilling….. No clear winner yet Find optimal technology for specific purpose First devices in production now (CMOS optical sensors for mobile phones) Large volume production imminent optical CMOS sensors memory chips processor – memory stacking ultrafast, low power processors

9. HEP applications‘hybrid pixel detecotors’ starting from classical hybrid pixels detector (a) add backside connectivity for higher fill factor (b) Multi tier ROIC for more functionality (c) high density interconnect to senor for smaller pitch, Reduced cost

10. Advantages even for single layer Conventional Layout 3D Layout Periphery, column logic, services Pixel area Make use of smaller feature size (gain space) -> move periphery in between pixels (can keep double column logic) -> backside contacts with vias possible -> no cantilever needed, 4-side abuttable

11. Digital section Analog section P-well NMOS N-well PMOS Deep N-well sensing electrode P-type epilayer or substrate 2D CMOS technology Digital section 1st tier Deep N-well sensing electrode Analog section e HEP applicationsCMOS sensors Starting from (advanced) MAPS PMOSFET in n-well acts as parasitic charge collection anode Reduced CCE Transfer most (if not all) of the PMOSFETs to 2nd tier High CCE More functionality

12. Furthermore • Many other technological approaches possible • Other technologies • MAPS on high resistivity (depletable) epi layer (large S/N, rad hardness) • SOI sensors (see talk by Junji Haba) • Combination of …. • Other applications (not necessarily HEP) • X-ray imagers: large memory for fast burst mode (XFEL) 4-side abuttable (large area without dead space) • Intelligent SiPMs single photon & single pixel resolution

13. Summary: R&D areas a) 3D technology improving CMOS MAPS sensors better CCE, full CMOS, more functionality, depleted substrate b) 3D multi tier ASICs for hybrid pixel detectors more functionality, smaller pixel size c) Improved interconnection alternative to bump bonding, backside contactivity, 4-side buttable However, R&D and prototyping turns out to be very expensive The basic problem is that always at some stage wafer level processing is required. This excludes MPW runs. Solution: create collaborations & networks to organize access to industry overcoming this obstacle Example; Fermilab 3D-IC (see talk be Valerio)