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Future devices for Information Technology

Future devices for Information Technology

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Future devices for Information Technology

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  1. Future devices for Information Technology 2003. 4. 4. Songcheol Hong

  2. Contents Electronic Devices (processing devices) High speed devices(digital, analog, RF) High power devices Memory devices Optical Devices QWLD, QDLD Optical communication devices GaN based Devices Display

  3. High speed devices Digital, Analog(RF) DSP upto Microwave frequencies IEEE MTT Vol. 50, N0. 3, 2002 p900

  4. Power dissipation/ MIPS

  5. Digital circuits expands to Analog domain

  6. Trends in Transmitter Architecture(Mobile) High Speed DSP (7GHz) DC-DC converter Vector Modulator DSP SDR One Chip Radio Supply voltage control Bias control

  7. Smart PA Heterodyne type Base/gate bias voltage control GaAs based PA Gate/base bias control

  8. Dynamic supply voltage (DSV) PA Direct conversion Supply Voltage Control  Dynamic Supply Control DSP clock speed ~ 10MHz GaAs PA + CMOS DC-DC converter SiGe BiCMOS

  9. Digital Predistorer Digital predistorter SiGe BiCMOS PA or CMOS switching PA

  10. Direct RF synthesis Direct RF Synthesis DSP clock speed ~ 7 GHz CMOS Switching PA and controller

  11. High speed Power Devices • MESFET/ HEMT  High Efficiency / high Linearity  Temperature stability  Negative bias  Develop Enhancement FET • MOSFET/LDMOS  Low Efficiency  Temperature Stability  Single bias

  12. HBT  High Efficiency / High Linearity  Single bias  High power density  Bad temperature stability  introduce Ballast R, careful bias circuit

  13. Typical InGaP Emitter HBT Structure

  14. Fig. 1. A cross-section of IBM's SiGe HBT structure, which was used to obtain a record-breaking ft value of 350 GHz. Credit: IBM.

  15. HBT comparison High power v.s. Digital

  16. Power transistor (FETs) Circuit design : Power combine : Unit transistor

  17. HBT with Ballast R ( Via hole and Air bridge) 12 finger Rb=50 8 finger Rb=50

  18. Power Cell 64 finger

  19. MOS power cell Conventional 구조 • Conventional 구조 • Poly gate와 drain metal의 저항이 클것으로 예상 • Source metal이 drain metal을 덮는 구조이므로 Cds가 클것으로 예상

  20. FET vs. HBT (size) HBT’s (being vertical in structure) consume less die area than an equivalent FET based production technology Example> take a PA line-up for GSM (Pout=35dBm, Vbat=3.2V)

  21. Ballasting • HBT devices must be BALLASTED to ensure thermal stability • Thermal run-away is avoided if a sufficiently large ballast resistance is placed in either the emitter or the base of the HBT • In a multi-finger array, one device may be hotter than other. The hotter device will experience a drop in Vbe (-2mV/oC) which will cause it to draw even more current from a fixed-base-voltage supply… thus it will get even hotter. The end result is finger burn-out

  22. Ballasting (conti…) • Three methods are available to ballast your circuit

  23. HBT bias circuit • Diode-bias and current-mirror circuits can be seen here: • • The key differences are: • - Diode bias requires the diode to draw current, which can be significant • Current mirror does not track as well over temperature • Current mirror has the “2  Vbe” reference-voltage issue

  24. CMOS and LDMOS power TR IEEE EDL, Vol. 21, No.2, p81, YueTan et al.

  25. High power LDMOS

  26. Conclusions I High speed digital and analog devices • Submicron CMOS(0.18um) is • covering upto 10Gbps and 10GHz range. • Submicron CMOS(0.05um) will be • covering upto 40 Gbps and 40 Ghz range. • Digital part will dominate Analog and RF • Finally, only power amp in RF with digital control • will survive • 5. LDMOS+CMOS will be a winner in Power applications • 6. SiGe may be used in high speed digital and • 10-60 GHz range RF. • 7. GaAs HBT is used in Power and Low noise application • 1- 40 GHz • 8. InP HBT and HEMT are used • in high frequencies(above 30Ghz)

  27. DRAM Figure 7.4: Simplified DRAM schematic.

  28. DRAM design rule

  29. Figure 7.7: Vertical stacked capacitor: Top-SEM photograph of the storage plate. Bottom-Solid model and grid of the simulated structure (only the material POLY1 is displayed).

  30. Figure 7.6: Process flow of the vertical stacked capacitor.

  31. FINFET

  32. Nono MOSFET

  33. Quantum Dot Flash memory

  34. FRAM Figure 1. Schematic cross section of a FRAM unit cell [1T/1C]

  35. Conclusion II Memory DRAM: Design rule becomes smaller, Ferroelectric Materials make C smaller, New Structures Nonvolatile Memory: Flash Nano-flash, QD flash FRAM MRAM

  36. QWLD, QDLD

  37. Self-assembled QDs

  38. AFM image of QD

  39. Figure 2. TEM micrograph showing the core of a 5-QWR Laser. The wires are positioned inside the 2D optical waveguide in an asymmetric configuration in order to maximize the overlap of the optical mode with Quantum wire grown on V groove

  40. LD, VCSEL, LED

  41. VCSEL

  42. Why Blue? GaN ?

  43. LD, LED ---Conclusion III Laser diode QW QD ---- High power LD VCSEL QW QD ---- Low threshold Current Blue light sources --- GaN Storage illumination

  44. Standard & Applications Optical communication devices Expected 10 Gigabit Ethernet solution • Method to overcome limit • 42.5 Gb/s WWDM with installed MMF & SMF • 10 Gb/s TDM with SMF & 1300nm LD Ref.) Tutorials, Agilent, 2000 OE conference