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A CPU MODULE FOR A SPACECRAFT CONTROLLER WITH HIGH THROUGHPUT SPACEWIRE INTERFACES

A CPU MODULE FOR A SPACECRAFT CONTROLLER WITH HIGH THROUGHPUT SPACEWIRE INTERFACES. ○Toru Sasaki, Minoru Nakamura, Tadashi Yoshimoto, Minoru Yoshida, Shoji Yoshikawa. MITSUBISHI ELECTRIC CORPORATION ADVANCED TECHNOLOGY R&D CENTER. International SpaceWire Conference 2008

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A CPU MODULE FOR A SPACECRAFT CONTROLLER WITH HIGH THROUGHPUT SPACEWIRE INTERFACES

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  1. A CPU MODULE FOR A SPACECRAFT CONTROLLER WITH HIGH THROUGHPUT SPACEWIRE INTERFACES ○Toru Sasaki, Minoru Nakamura, Tadashi Yoshimoto, Minoru Yoshida, Shoji Yoshikawa MITSUBISHI ELECTRIC CORPORATION ADVANCED TECHNOLOGY R&D CENTER International SpaceWire Conference 2008 4th-6th November 2008 Nara, Japan Nara Prefectural New Public Hall

  2. Table of Contents Melco standard small satellite Spacecraft Controller • Introduction • CPU module • DMA Controller • Evaluation • Conclusion CPU module FPGA IP Evaluation PCI bus Controller SpaceWire Controller IP DMA Controller

  3. Payload Introduction Melco Standard Small Satellite System (200kg-class) Missions ○Science, Deep Space ○Earth Observation - high performance mission Concepts ○ Low Cost, Short Term Integration,Mission Flexibility Science Spacecraft Controller CPU module with high throughput SpaceWire CPU module

  4. CPU module 33MHz Clock 50MHz Clock FPGA function diagram Watch Dog Timer PCI Bus Bridge Controller GPIO SpW Controller DMA Controller Interrupt Controller Serial I/F Controller CPU module function ○ DH (Data Handling) ○ AOC (Attitude and Orbit Control) ○ SM (Satellite Management) CPU module CPU module FPGA Components System Memory PCI CPU SpaceWire • FPGA Function • ○Various IPs • Interrupt Controller, • DMA Controller, • SpaceWire Controller ※DMA : Direct Memory Access : DMA data path

  5. 33MHz Clock 50MHz Clock FPGA function diagram Watch Dog Timer PCI Bus Bridge Controller GPIO SpW Controller DMA Controller Interrupt Controller Serial I/F Controller DMA Controller Feature CHARACTERISTICS of DMA Controller ○ 8 channels - 4 channels for sending 4 channels for receiving ○ Burst transfer mode - 2, 4 and 8 words (1 word = 4 bytes) ○ Double Register Mode → Next slide B registers A registers EOP SIGNAL 0ch Buffer Controller 8 word Buffer DATA Address Decoder CH0 From SpaceWire Controller CH1 Data Path Controller CH7 ※EOP: End of SpaceWire Packet

  6. Double Register Mode A set • Double Register Mode • ○ 2 sets of registers • You can set another set of registers • even while DMA controller is transferring data. • ○ A/B change by DMA completion or EOP • - Automatic change • - Separate management of • SpaceWire packets Control Register Address Register Count Register B set Control Register Address Register Count Register expiration of A count register or EOP arrival DMA active waiting A B expiration of B count register or EOP arrival waiting DMA active A B DMA active waiting expiration of A count register or EOP arrival A B

  7. Evaluation Purpose ○Test the efficiency of Double Register Mode Condition ○Loop back wiring ○Link Speed = 10Mbps ○Lowered CPU Performance (~1MIPS) to emphasize the effect CPU module SpaceWire FPGA CPU(1MIPS) TX RX • Measurement item • 1. Transfer rate [Mbps] • - Data Size[KB] / Time[ms]×10-6 • 2. Comparison • Double Register Mode VS • Single Register Mode • - At various size of SpW packet Loop Back send and receive 2000 SpW packets Send Data Receive Data SRAM ※burstlength = 8

  8. Result Transfer Rate [Mbps] Double Register Mode • Results • Transfer rate • 7.5 Mbps (max) • 93% of full performance • 2. Comparison • Double/Single = 1.5 • Less effective at short • packet 1.5 times Single Register Mode length of SpW packet [bytes] • S/W setup time < DMA transfer time long SpW packet DMAC DMA transfer time for A reg DMA transfer time for B reg GOOD Performance! Time S/W setup time start A start B start A • S/W setup time > DMA transfer time short SpW packet Wait Wait DMAC DMA transfer time for A reg DMA transfer time for B reg DMA transfer timer for A reg Poor performance! Time setup time S/W start A start B start A We want to make the SpaceWire link speed faster .

  9. Conclusion • ○ Melco has developed a CPU module with SpaceWire. • ○ The DMA Controller enhanced the efficiency of SpaceWire • with Double Register Mode. • ○ Evaluation of Double Register Mode • - 7.5 Mbps (max.) @ 10Mbps link, • - 93% of full performance@1MIPS CPU • - 1.5 times faster than Single Register Mode • ○ We have a plan to raise SpaceWire link speed and search • the performance limit.

  10. Thank you for your attention Thank you for your attention

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