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Switching Units

Switching Units

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Switching Units

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  1. Switching Units

  2. Types of switching elements • Telephone switches • switch samples • Datagram routers • switch datagrams • ATM switches • switch ATM cells INPUTS OUTPUTS

  3. Look Inside a Router Two key router functions: run routing algorithms/protocol (RIP, OSPF, BGP) switching datagrams from incoming to outgoing ports 3

  4. Repeaters, bridges, routers, and gateways • Repeaters/Hubs: at physical level (L1) • Bridges: at datalink level (L2) • based on MAC addresses • discover attached stations by listening • Routers: at network level (L3) • participate in routing protocols • Application level gateways: at application level (L7) • treat entire network as a single hop • Gain functionality at the expense of forwarding speed • for best performance, push functionality as low as possible

  5. Types of services • Packet vs. circuit switches • packets have headers and samples don’t • Connectionless vs. connection oriented • connection oriented switches need a call setup • setup is handled in control plane by switch controller • connectionless switches deal with self-contained datagrams

  6. Other switching unit functions • Participate in routing algorithms • to build routing tables • Next Lecture! • Resolve contention for output trunks • buffer scheduling • Previous Lecture! • Admission control • to guarantee resources to certain streams

  7. Requirements • Capacity of switch is the maximum rate at which it can move information, assuming all data paths are simultaneously active • Primary goal:maximize capacity • subject to cost and reliability constraints • Circuit switch must reject call if can’t find a path for samples from input to output • goal: minimize call blocking • Packet switch must reject a packet if it can’t find a buffer to store it awaiting access to output trunk • goal: minimize packet loss • Subgoal:Don’t reorder packets

  8. Internal switching • In a circuit switch, path of a sample is determined at time of connection establishment • No need for a sample header--position in frame is enough • In a packet switch, packets carry a destination field • Need to look up destination port on-the-fly • Datagram • lookup based on entire destination address • Cell • lookup based on VCI – used as an index to a table • Other than that, switching units are very similar

  9. Blocking in packet switches • Can have both internal and output blocking • Internal • no path to output • Example: head of line blocking. • Output • output link busy • If packet is blocked, must either buffer or drop it

  10. Dealing with blocking • Overprovisioning • internal links much faster than inputs • Buffers • at input or output • Backpressure • if switch fabric doesn’t have buffers, prevent packet from entering until path is available • Parallel switch fabrics • increases effective switching capacity

  11. Three generations of packet switches • Different trade-offs between cost and performance • Represent evolution in switching capacity, rather than in technology • With same technology, a later generation switch achieves greater capacity, but at greater cost • All three generations are represented in current products

  12. linecard linecard First generation switch • Most Ethernet switches and cheap packet routers • Bottleneck can be CPU, host-adaptor or I/O bus, depending computer CPU queues in memory linecard

  13. Second generation switch • Port mapping intelligence in line cards • Bottleneck is the bus (or ring) computer bus front end processors or line cards

  14. Third generation switches • Third generation switch provides parallel paths (fabric) OLC ILC NxN packet switch fabric OUT OLC IN ILC OLC ILC control

  15. Third generation (contd.) • Features • self-routing fabric • output buffer is a point of contention • unless we arbitrate access to fabric • potential for unlimited scaling, • as long as we can resolve contention for output buffer

  16. Switching - Fabric

  17. Switching: abstract model Number of connections: from few (4 or 8) to huge (100K)

  18. 1 2 N 1 2 N De-Mux 1 2 N MUX Multiplexors and demultiplexors • Multiplexor: aggregates sessions • N input lines • Output runs N times as fast as input • Demultiplexor: distributes sessions • one input line and N outputs that run N times slower • Can cascade multiplexors

  19. D E M U X M U X TSI Time division switching • Key idea: when demultiplexing, position in frame determines output link • Time division switching interchanges sample position within a frame: • Time slot interchange (TSI)

  20. 4 3 2 1 Time Slot Interchange (TSI) : example sessions: (1,3) (2,1) (3,4) (4,2) 1 2 3 4 2 1 4 2 3 1 4 2 1 3 3 4 Read and write to shared memory in different order

  21. TSI • Simple to build. • Multicast: easy (why?) • Limit is the time taken to read and write to memory • For 120,000 telephone circuits • Each circuit reads and writes memory once every 125 ms. • Number of operations per second : 120,000 x 8000 x2 • each operation takes around 0.5 ns => impossible with current technology • Need to look to other techniques

  22. i n p u t s outputs Space division switching • Each sample takes a different path through the switch, depending on its destination • Crossbar: Simplest possible space-division switch • Crosspoints can be turned on or off

  23. 1 2 3 4 4 1 2 3 Crossbar - example sessions: (1,2) (2,4) (3,1) (4,3) inputs output

  24. Crossbar • Advantages: • simple to implement • simple control • strict sense non-blocking • Multicast • Single source multiple destination ports • Drawbacks • number of crosspoints, N2 • large VLSI space • vulnerable to single faults

  25. MUX 1 2 1 TSI 1 2 2 3 MUX 4 3 4 3 TSI 4 DeMux DeMux Time-space switching • Precede each input trunk in a crossbar with a TSI • Delay samples so that they arrive at the right time for the space division switch’s schedule Crosspoint: 4 (not 16) memory speed : x2 (not x4)

  26. 1 2 1 2 3 4 3 4 Finding the schedule • Build a routing graph • nodes - input links • session connects an input and output nodes. • Feasible schedule • Computing a schedule • compute perfect matching.

  27. time 1 time 2 2 1 2 1 TSI 3 4 4 3 3 1 2 4 Time-Space: Example TSI Internal speed = double link speed

  28. Internal Non-Blocking Types • Re-arrangeable • Can route any permutation from inputs to outputs. • Strict sense non-blocking • Given any current connections through the switch. • Any unused input can be routed to any unused output. • Wide sense non-blocking. • There exists a specific routing algorithm, s.t., • for any sequence of connections and releases, • Any unused input can be routed to any unused output, • assuming all the sequence was served by the routing algorithm.

  29. Circuit switching - Space division • graph representation • transmitter nodes • receiver nodes • internal nodes • Feasible schedule • edge disjoint paths. • cost function • number of crosspoints (complexity of AxB is AB) • internal nodes

  30. Crossbar - example 1 2 3 4 4 1 2 3

  31. Another Example inputs outputs

  32. Another Example sessions: (1,3) (2,6) (3,1) (4,4) (5,2) (6,5) inputs outputs

  33. 2x2 2x2 2x2 Clos Network Clos(N, n , k) : N - inputs/outputs; cross-points: 2 (N/n)nk + k(N/n)2 kxn nxk (N/n)x(N/n) 2x2 3x3 N=6 n=2 k=2 2x2 N 3x3 2x2 k N/n N/n

  34. Clos Network - strict sense non-blocking • Holds for k  2n-1 • Proof Methodology: • Recall: IF [A,B  S and |A|+|B| > |S|] then A∩ B≠Ø • S= The k middle switches • A = middle switches reachable from the inputs • B = middle switches reachable from the outputs • Our case: • |S|=k • |A| ≥ k-(n-1) • |B| ≥ k-(n-1)

  35. n-1 k x n n-1 n x k Clos Network - strict sense non-blocking • Holds for k  2n-1 • Proof: • Consider an idle input and output • Input box connected to at most n-1 middle layer switches • output box connected to at most n-1 middle layer switches • There exists an ”unused" middle switch good for both.

  36. 2x3 4x4 3x2 2x3 4x4 3x2 N=8 n=2 k=3 2x3 3x2 4x4 2x3 3x2 Example Clos(8,2,3) Need to route a new call

  37. kxn nxk (N/n)x(N/n) 2x2 3x3 2x2 N=6 n=2 k=2 2x2 2x2 3x3 2x2 2x2 Clos Network Why is k=n internally blocking?

  38. 1 2 1 2 3 4 3 4 Clos Network - re-arrangable • Holds for k  n • Proof: • Consider the routing graph. • find a perfect matching. • route the perfect matching through a single middle switch! • remaining network is Clos(N-N/n,n-1,k-1) • summary: • smaller circuit • weaker guarantee • Multicast ?

  39. Recursive Construction: basis The basic element: The dimension: r=0 The two states:

  40. Recursive Construction: Benes Network r-1 dimension N/2 size r-1 dimension N/2 size

  41. Example 16x16

  42. Benes Networks • Symmetry • Size: • F(N) = 2(N/2)*4 + 2F(N/2) = O(N log N) • Rearrangable • Clos network with k=2 n=2 • Proof I: • Build routing graph. • Find 2 matchings • route one in the upper Benes and the other in the lower.

  43. Greedy permutation routing • Start with an arbitrary node i1 • set i1 to upper. • At the output, o1 , a new constraint, • set o2 to lower. • Continue until no new constraint. • Completing a cycle. • Continue until done. • Solve for the upper and lower Benes recursively.

  44. Example: Benes Network for r=2 I1 1 2 3 4 5 6 7 8 I2 level 0 switches level 2r switches

  45. Example 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ) ( I1 1 2 3 4 5 6 7 8 I2 level 0 switches level 2r switches

  46. Example 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ) ( I1 1 2 3 4 5 6 7 8 I2 level 0 switches level 2r switches

  47. Example 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ) ( I1 1 2 3 4 5 6 7 8 I2 level 0 switches level 2r switches

  48. Example 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ) ( I1 1 2 3 4 5 6 7 8 I2 level 0 switches level 2r switches

  49. CRS-1 Switch Fabric Overview 50 Gbps136 Bytes cells 100 Gbps/LC(2)(2.5X Speedup) Fabric Chassis 40 Gbps 8 of 8 8 16 S1 S2 S3 2 of 8 2 2 1 of 8 1 1 Line Card Line Card S1 S2 S3 2 LEVELS OF PRIORITY HP Low latency traffic LP Best effort traffic MULTICAST SUPPORT 1M multicast groups S1 S2 S3 1296 x 1296 buffered non-blocking switchMulti-stage Interconnect—3 Stage Benes topology

  50. Basic Router Architecture 3 Main components: Line cards,Switching mechanism, Route Processor(s), Routing Applications Forwarding Component Interconnect Control Components