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SAR ATR Challenge Problem Update SLAAC Retreat March 1999

SAR ATR Challenge Problem Update SLAAC Retreat March 1999. Brian K. Bray Sandia National Laboratories bkbray@sandia.gov. Joint STARS ‘97 SAR ATR Pipeline. Sandia National Labs. SAR Image. Annotated SAR Image. T72. T72. *Not Joint STARS imagery. Identification. PGA. Detection.

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SAR ATR Challenge Problem Update SLAAC Retreat March 1999

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  1. SAR ATRChallenge Problem UpdateSLAAC RetreatMarch 1999 Brian K. Bray Sandia National Laboratories bkbray@sandia.gov

  2. Joint STARS ‘97 SAR ATR Pipeline Sandia National Labs SAR Image Annotated SAR Image T72 T72 *Not Joint STARS imagery Identification PGA Detection Joint STARS Advance Workstation (JAWS) ATR Results Display ESAR Image Focus of Attention Indexer (SLD) Belief Management (Fusion Executive) MPM MSE CRM LPM Hardware Used DARPA EHPC Hardware Mercury PowerPC Multicomputer HPSC Alpha WS

  3. Weight (lbs.) 17.5 354 1680 lbs. ft3 W 7 124 453 3.5 (5 VME chassis) (2 VME chassis) 50 160 ATR System Hardware Evolution Sandia National Labs For: 1 Mpixel/sec with 6 target configurations (targets in-the-clear scenario) • 1997-98 Flight System: • early two-level multiprocessor • Baseline 1996 System: • Systolic, SIMD, very early two-level multiprocessor/DSP • 1999 TCTA System: • maturing two-level multiprocessor Power, Volume, Weight Product (W- ft3 -lbs.) Power (W) Volume (ft3) 10,407,600 26X reduction W- ft3 -lbs 371X reduction 393,204 28,000 Current two-level multiprocessor configuration implements algorithms with better performance and significantly lower power, size, and weight versus baseline implementation

  4. * SAR Area Coverage Rate (sqnm / day @1 ft Res.) 1000 40,000 40X (FOA, Number of Target Classes 6 30 5X (Indexer, Ident.) Level / Difficulty of CC&D Low High 100X (Indexer) 10X (Ident.) * Corresponds to a data rate of 40 Megapixels / sec Surveillance Challenge Problem - SAR / ATR 40,000 sqnm / day @ 1 ft. Resolution System Parameter Current Challenge Scale Factor Indexer, Ident.)

  5. SLAAC’s Competition • Quad PowerPC G3 boards (now - end ‘99) • CSPI 2741 • PPC750@400Mhz w/1MB L2$, 64MB/node • Mercury • PPC750@375Mhz w/1MB L2$, 128MB/node • Quad PowerPC G4 boards (‘00 - ?) • PowerPC G5 boards (?)

  6. ATR Latency Tests Sandia National Labs

  7. MPI Bandwidth Benchmark Sandia National Labs

  8. MPI Latency Benchmark Sandia National Labs

  9. Deployable Reference Platform (DRP) Myrinet Diagram Sandia National Labs Host Workstation Myricom FPGA Motorola SBC & CSPI 2741 CSPI 2741

  10. Myricom FPGA Board Implementing SLD • It works, but • implementation is out-of-date with current algorithm • some calculation errors • truncation instead of rounding in an integer divide? • Reliability is poor • Power-up and LANai/FPGA load reliability is poor • poor reset circuitry? • Flashing LEDs for status was extremely helpful • Need to work on extra buffering in the host node so the FPGA worker nodes always have work • Coprocessor model for low-level control of FPGA accelerators (instead of remote LANai method of Myricom FPGA board) is still the way to go

  11. Near-Term Performance Goal for SLAAC • 100X over ‘96 baseline system by using latest EHPC and ACS technology • 2 Mpixels/sec for 6 partially obscured target types • ~20X there with COTS two-level multicomputers (EHPC) • need ~5X more from ACS • need ~10X from ACS on FOA and Indexing • some performance loss from • not all operations are implemented in ACS • overhead in control of ACS

  12. Proposal for what to do for Fall SAR ATR Lab Demo? • Use embedded SLAAC2 boards • SLD? • hosted on CSPI 2X41S carrier boards • shows embedded capability • Use latest generation COTS PCI FPGA board • FOA, CDI? • use Annapolis Micro Systems Wildstar? • Add two embedded PC chassis to DRP to host the PCI FPGA cards • with Myrinet PCI card • which OS? (Myricom MCP drivers for Linux and Solaris x86, what about Wildstar board?) • doesn’t show 6U VME insertion but will show ACS performance gains

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